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Mostrati risultati da 1 a 20 di 77
Titolo Data di pubblicazione Autore(i) File
Accurate power estimation model for CMOS adders optimization 1-gen-2004 Perri, Stefania; Frustaci, F; Corsonello, Pasquale
Impact of oxide thickness on performances of logic circuits: a predictive simulation study 1-gen-2005 Frustaci, F.; Corsonello, Pasquale
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 1-gen-2006 Frustaci, F; Corsonello, Pasquale; Perri, Stefania; Cocorullo, Giuseppe
Leakage Energy Reduction Techniques in Deep Submicron Cache Memories: A Comparative Study 1-gen-2006 Frustaci, F; Corsonello, Pasquale; Perri, Stefania; Cocorullo, Giuseppe
Techniques for leakage energy reduction in deep submicrometer cache memories 1-gen-2006 Frustaci, F; Corsonello, Pasquale; Perri, Stefania; Cocorullo, Giuseppe
A new noise-tolerant dynamic logic circuit design 1-gen-2007 Frustaci, F; Corsonello, Pasquale; Cocorullo, Giuseppe
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 1-gen-2008 Frustaci, F; Corsonello, Pasquale; Perri, Stefania; Cocorullo, Giuseppe
Designing High-Speed Adders in Power-Constrained Environments 1-gen-2009 Frustaci, F; Lanuzza, Marco; Zicari, P; Perri, Stefania; Corsonello, Pasquale
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 1-gen-2009 Frustaci, F; Corsonello, Pasquale; Perri, S; Cocorullo, Giuseppe
Low-power split-path data-driven dynamic logic 1-gen-2009 Frustaci, F.; Lanuzza, Marco; Zicari, P.; Perri, Stefania; Corsonello, Pasquale
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 1-gen-2009 Lanuzza, Marco; Zicari, P; Frustaci, F; Perri, Stefania; Corsonello, Pasquale
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 1-gen-2009 Frustaci, F.; Corsonello, Pasquale; Perri, Stefania; Cocorullo, G.
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 1-gen-2010 Lanuzza, Marco; Zicari, P; Perri, Stefania; Frustaci, F; Corsonello, Pasquale
A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder 1-gen-2010 Frustaci, F; Lanuzza, Marco
A new low-power high-speed single-clock-cycle binary comparator 1-gen-2010 Frustaci, F.; Perri, Stefania; Lanuzza, Marco; Corsonello, Pasquale
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 1-gen-2010 Lanuzza, Marco; Zicari, P.; Frustaci, F.; Perri, Stefania; Corsonello, Pasquale
Design and evaluation of high-speed energy-aware carry skip adders 1-gen-2010 DE ROSE, R; Lanuzza, Marco; Frustaci, F.
A low-leakage single ended 6T SRAM cell 1-gen-2010 Solanki, S.; Frustaci, F.; Corsonello, Pasquale
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 1-gen-2010 Lanuzza, M; De Rose, R; Frustaci, F; Perri, S; Corsonello, P
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 1-gen-2011 Lanuzza, Marco; Frustaci, F; Perri, Stefania; Corsonello, Pasquale
Mostrati risultati da 1 a 20 di 77
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