This paper describes anew efficient 32x32 Single Instruction Multiple Data (SIMD) multiplier suitable for the multimedia extension of FPGA-based processors. The proposed circuit can adapt itself to 32-, 16-, and 8-bit operands widths avoiding time and power consuming reconfiguration. When implemented in an XCV400 device, the multiplier here described reaches a running frequency of about 97 MHz with an energy dissipation of just 20 mW/MHz. Comparisons with previously proposed SIMD multipliers for FPGA-based designs demonstrate that the new circuit allows the best area-time-power trade-off to be obtained.

This paper describes anew efficient 32x32 Single Instruction Multiple Data (SIMD) multiplier suitable for the multimedia extension of FPGA-based processors. The proposed circuit can adapt itself to 32-, 16-, and 8-bit operands widths avoiding time and power consuming reconfiguration. When implemented in an XCV400 device, the multiplier here described reaches a running frequency of about 97 MHz with an energy dissipation of just 20 mW/MHz. Comparisons with previously proposed SIMD multipliers for FPGA-based designs demonstrate that the new circuit allows the best area-time-power trade-off to be obtained.

SIMD multipliers for accelerating embedded processors in FPGAs

PERRI, Stefania;CORSONELLO, Pasquale
2006-01-01

Abstract

This paper describes anew efficient 32x32 Single Instruction Multiple Data (SIMD) multiplier suitable for the multimedia extension of FPGA-based processors. The proposed circuit can adapt itself to 32-, 16-, and 8-bit operands widths avoiding time and power consuming reconfiguration. When implemented in an XCV400 device, the multiplier here described reaches a running frequency of about 97 MHz with an energy dissipation of just 20 mW/MHz. Comparisons with previously proposed SIMD multipliers for FPGA-based designs demonstrate that the new circuit allows the best area-time-power trade-off to be obtained.
2006
This paper describes anew efficient 32x32 Single Instruction Multiple Data (SIMD) multiplier suitable for the multimedia extension of FPGA-based processors. The proposed circuit can adapt itself to 32-, 16-, and 8-bit operands widths avoiding time and power consuming reconfiguration. When implemented in an XCV400 device, the multiplier here described reaches a running frequency of about 97 MHz with an energy dissipation of just 20 mW/MHz. Comparisons with previously proposed SIMD multipliers for FPGA-based designs demonstrate that the new circuit allows the best area-time-power trade-off to be obtained.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/142446
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