This paper presents VLSI circuits for Variable Block-Size Motion Estimation based on the Multiplication- Free Weighted SAD. Comparisons with existing SAD-based circuits demonstrate that higher accuracy is achieved without compromising speed performance, but resources requirements can significantly increase. Using a 90nm 1V CMOS technology, a running frequency higher than 1GHz and average power consumption lower than 100uW/MHz are reached.
VLSI Circuits for Accurate Motion Estimation
PERRI, Stefania;CORSONELLO, Pasquale;COCORULLO, Giuseppe
2010-01-01
Abstract
This paper presents VLSI circuits for Variable Block-Size Motion Estimation based on the Multiplication- Free Weighted SAD. Comparisons with existing SAD-based circuits demonstrate that higher accuracy is achieved without compromising speed performance, but resources requirements can significantly increase. Using a 90nm 1V CMOS technology, a running frequency higher than 1GHz and average power consumption lower than 100uW/MHz are reached.File in questo prodotto:
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