Embedded Hardware to Synchronize the Triggering of Measurement Instrument Networking

The research is devoted to investigate about the coordination in the time domain of the operations executed by the Measurement Instruments (MIs) connected by Hardware Interface (HI) to the node of the Distributed Measurement System. A new architecture of HI is proposed to trigger the MIs in order to (i) avoid the random effects of concurrency of the software processes running on PC, (ii) reduce the upper bound of the execution time of the procedure running on Real Time Operating System, and (iii) shorten the random time delay to detect the trigger condition, introduced by the polling cycle on the Programmable Logic Device (PLD). The proposed architecture of the HI includes the PLD as wireless interface, and the board designed to synchronize the trigger. It is equipped by PIC, Counter block, and Clk block. Experimental tests validate the HI pointed out and the proposed strategy to trigger the MIs in the synchronized modality.