An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on Gardner Timing Error Detector

This paper presents an efficient and optimized FPGA implementation of a complete digital Symbol Timing Recovery (STR) architecture based on a Digital PLL loop structure. Matlab modelling first and a complete hardware communication system test after, reveal that the implemented STR circuit offers the best performances compared with the other implemented works present in literature. When implemented on an Xilinx Virtex-2P XC2VP7 FF672 FPGA chip the proposed STR circuit occupies just 138 slices, uses 2 embedded multipliers and reaches a clock frequency of 106 MHz; a symbol rate of 10 Msymbol/sec can be reached when 10 samples per symbol are employed. The obtained results are promising for its use in Software Defined Radio System applications.