This paper presents a novel high-speed parallel multiplier based on 3-bit-scan without overlapping bits. The proposed multiplier is able to elaborate both signed and unsigned operands and it. is suitable for both full-custom and standard-cells based VLSI implementations. When realized using the ST 90nm CMOS standard-cells library, the 8×8 version of the novel multiplier exhibits a worstcase delay of only 0.93ns and dissipates ~27uW/MHz.
Parallel Multipliers using 3-bit-scan without overlapping bits
PERRI, Stefania;CORSONELLO, Pasquale
2007-01-01
Abstract
This paper presents a novel high-speed parallel multiplier based on 3-bit-scan without overlapping bits. The proposed multiplier is able to elaborate both signed and unsigned operands and it. is suitable for both full-custom and standard-cells based VLSI implementations. When realized using the ST 90nm CMOS standard-cells library, the 8×8 version of the novel multiplier exhibits a worstcase delay of only 0.93ns and dissipates ~27uW/MHz.File in questo prodotto:
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