This paper presents a new standard-cells based low-power sub- nanosecond 64-bit adder. For the first time, in the proposed circuit a hybrid quaternary carry-look-ahead carry-skip tree is exploited to quickly compute carries into appropriate positions. Moreover, sum units organized as carry-increment blocks are used. When realized with the standard-cell libraries of the ST 0.18um 1.8 V CMOS technology, the new adder exhibits a computational delay of just 980ps, an average power dissipation of 27mW @ 500MHz and a silicon area occupancy of about 0.015mm2.
A Low-Power Sub-Nanosecond Standard-Cells Based Adder
PERRI, Stefania;CORSONELLO, Pasquale;
2003-01-01
Abstract
This paper presents a new standard-cells based low-power sub- nanosecond 64-bit adder. For the first time, in the proposed circuit a hybrid quaternary carry-look-ahead carry-skip tree is exploited to quickly compute carries into appropriate positions. Moreover, sum units organized as carry-increment blocks are used. When realized with the standard-cell libraries of the ST 0.18um 1.8 V CMOS technology, the new adder exhibits a computational delay of just 980ps, an average power dissipation of 27mW @ 500MHz and a silicon area occupancy of about 0.015mm2.File in questo prodotto:
Non ci sono file associati a questo prodotto.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
