The dynamic power consumption of a complementary metal-oxide-semiconductor (CMOS) gate driving a resistance-inductance-capacitance (RLC) transmission line is investigated in this paper. The closed-form solution for the dynamic power has been carried out by a simple time domain model for input impedance of a lossy transmission line, specifically developed to be used in conjunction with MOS macromodels. The proposed solution agrees with circuit simulations within 1% error for a wide range of line parameters, and it demonstrates how power dissipation localized in the wire resistance may be a significant aliquot of the global power consumption.
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines
CORSONELLO, Pasquale;COCORULLO, Giuseppe;PERRI, Stefania;
2001-01-01
Abstract
The dynamic power consumption of a complementary metal-oxide-semiconductor (CMOS) gate driving a resistance-inductance-capacitance (RLC) transmission line is investigated in this paper. The closed-form solution for the dynamic power has been carried out by a simple time domain model for input impedance of a lossy transmission line, specifically developed to be used in conjunction with MOS macromodels. The proposed solution agrees with circuit simulations within 1% error for a wide range of line parameters, and it demonstrates how power dissipation localized in the wire resistance may be a significant aliquot of the global power consumption.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
