Variable precision multipliers for FPGA-based reconfigurable computing systems

This paper describes a new efficient multiplier for FPGA-based variable precision processors. The circuit here proposed can adapt itself at run-time to different data wordlengths avoiding time and power consuming reconfiguration. This is made possible thanks to the introduction of on purpose designed auxiliary logic, which enables the new circuit to operate in SIMD fashion and allows high parallelism levels to be guaranteed when operations on lower precisions are executed. The proposed circuit has been characterised using VIRTEX XILINX devices, but it can be efficiently used also in others FPGA families.