A novel architecture of adder with accumulation register here called Adder Accumulator (AAC) is presented. When used for the implementation of an MAC, it drastically reduces the delay of the final adder portion with a very small extra area consumption. The novel architecture merges the adder block and the accumulator register present In the MAC operator furnishing the possibility to use two separate n/2 bit adders instead of the n bit adder generally employed to accumulate the n bit MAC result.
An optimized Adder accumulator for high speed MACs
PERRI, Stefania;CORSONELLO, Pasquale;COCORULLO G.
2005-01-01
Abstract
A novel architecture of adder with accumulation register here called Adder Accumulator (AAC) is presented. When used for the implementation of an MAC, it drastically reduces the delay of the final adder portion with a very small extra area consumption. The novel architecture merges the adder block and the accumulator register present In the MAC operator furnishing the possibility to use two separate n/2 bit adders instead of the n bit adder generally employed to accumulate the n bit MAC result.File in questo prodotto:
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