In integrated all-digital FPGA based communication systems bit synchronization is a fundamental operation for the best symbol detection. In this paper a highly flexible Early-Late Gate implementation is proposed. It is optimized for low resource consumption in FPGA implementations.
An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs
CORSONELLO, Pasquale;PERRI, Stefania
2006-01-01
Abstract
In integrated all-digital FPGA based communication systems bit synchronization is a fundamental operation for the best symbol detection. In this paper a highly flexible Early-Late Gate implementation is proposed. It is optimized for low resource consumption in FPGA implementations.File in questo prodotto:
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