This paper proposes a fast adder structure for Xilinx Virtex-5 FPGAs. The generic n-bit adder is split into two n/2-bit adders. The portion which computes the n/2 most significant sum bits receives the carry input signal from a purpose-designed fast carry generator instead of the n/2-bit adder generating the least significant sum bits. This allows outperforming the ripple carry adders implemented in the chosen FPGA family. The fast carry chain propagation is reached by optimizing the use of 6-input LUTs together with the dedicated MUXCY resources available in the Virtex-5 FPGA chip. A 64-bit adder designed as proposed here is ∼11% and ∼35% faster than the standard carry chain adder and the DSP-based adder implementation, respectively.
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