This paper presents a novel architecture optimized for realizing efficient absolute difference circuits in Virtex-5 FPGA devices. The proposed structure efficiently uses the 6- input look-up-tables available within the chosen devices family to maximize speed performance and to minimize the amount of occupied resources. In comparison with the DSP- and the LUT-based absolute difference circuits automatically synthesized and mapped by the ISE development tool the proposed structure is up to 40% cheaper and up to 61.5% faster.
Efficient Absolute Difference Circuits in Virtex-5 FPGAs
PERRI, Stefania;CORSONELLO, Pasquale
2010-01-01
Abstract
This paper presents a novel architecture optimized for realizing efficient absolute difference circuits in Virtex-5 FPGA devices. The proposed structure efficiently uses the 6- input look-up-tables available within the chosen devices family to maximize speed performance and to minimize the amount of occupied resources. In comparison with the DSP- and the LUT-based absolute difference circuits automatically synthesized and mapped by the ISE development tool the proposed structure is up to 40% cheaper and up to 61.5% faster.File in questo prodotto:
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