Area- And Power-Reduced Standard-Cell Spanning Tree Adders

This paper presents new fast, low-cost Spanning Tree adders for double-precision mantissas (IEEE 754-floating point standard). The new adders are modifications of conventional Spanning Tree adders. The improvements in the proposed circuits are made possible by replacing high power and area consuming block summation units used in the conventional architectures with newly designed low-area and lowpower modules. A 56-bit adder designed as described here and fabricated using AMS 0.35μm CMOS Standard Cells at 3.3V supply voltage shows a worst case delay of about 4.4ns, a maximum power dissipation of only 613μW/MHz and a silicon area requirement less than 0.2 mm2. The results obtained here are fully expected to be scalable, especially in standard cell technologies.