This paper presents a novel FPGA-based stereo matching system. The proposed circuit operates on 512×512 stereo images with a maximum disparity of 255. It achieves a 286MHz running frequency and a frame rate of 25.6 f/s.
Sad-Based Stereo Matching Circuit for FPGAs
PERRI, Stefania;CORSONELLO, Pasquale
2006-01-01
Abstract
This paper presents a novel FPGA-based stereo matching system. The proposed circuit operates on 512×512 stereo images with a maximum disparity of 255. It achieves a 286MHz running frequency and a frame rate of 25.6 f/s.File in questo prodotto:
Non ci sono file associati a questo prodotto.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
