The research is devoted to investigate about the coordination in the time domain of the operations executed by the Measurement Instruments (MIs) connected by Hardware Interface (HI) to the node of the Distributed Measurement System. A new architecture of HI is proposed to trigger the MI. The new HI (i) avoids the random effects of concurrency of the software processes running on PC, (ii) reduces the upper bound of the execution time of the procedure by using Real Time Operating System, and (iii) reduces the random causes of delay, introduced by the polling cycle on the Programmable Logic Device (PLD), to detect the trigger condition. The proposed architecture of the HI includes the PLD as wireless interface, and the board equipped by PIC, Counter block, and Clk block. The board is designed to reduce the random variation of the time delay and to avoid the polling cycle to check the trigger condition. From the analysis of the HI the models of the synchronization time delay and its variation are pointed out in order to evaluate the effects of each cause affecting the execution of the trigger command for the MI. This evaluation furnishes the information to point out the adequate strategy to reduce the random variation of the time delay to synchronize MIs. Experimental tests validate the HI pointed out and the proposed strategy.

Reduction of the Random Variation of Time Delay to Synchronize Measurement Instruments

Lamonaca F
2010

Abstract

The research is devoted to investigate about the coordination in the time domain of the operations executed by the Measurement Instruments (MIs) connected by Hardware Interface (HI) to the node of the Distributed Measurement System. A new architecture of HI is proposed to trigger the MI. The new HI (i) avoids the random effects of concurrency of the software processes running on PC, (ii) reduces the upper bound of the execution time of the procedure by using Real Time Operating System, and (iii) reduces the random causes of delay, introduced by the polling cycle on the Programmable Logic Device (PLD), to detect the trigger condition. The proposed architecture of the HI includes the PLD as wireless interface, and the board equipped by PIC, Counter block, and Clk block. The board is designed to reduce the random variation of the time delay and to avoid the polling cycle to check the trigger condition. From the analysis of the HI the models of the synchronization time delay and its variation are pointed out in order to evaluate the effects of each cause affecting the execution of the trigger command for the MI. This evaluation furnishes the information to point out the adequate strategy to reduce the random variation of the time delay to synchronize MIs. Experimental tests validate the HI pointed out and the proposed strategy.
9781424428335
measurement
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/20.500.11770/314582
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