A new methodology for realising efficient multiply architectures for FPGAs is presented. The proposed strategy can be recursively applied to realise larger multipliers. Compared to proprietary macroblocks usually furnished within FPGA development tools, the new approach is more than 45% cheaper and more than 25% faster.
Efficient Recursive Multiply Architecture for FPGAs
PERRI, Stefania;CORSONELLO, Pasquale;COCORULLO, Giuseppe
2005-01-01
Abstract
A new methodology for realising efficient multiply architectures for FPGAs is presented. The proposed strategy can be recursively applied to realise larger multipliers. Compared to proprietary macroblocks usually furnished within FPGA development tools, the new approach is more than 45% cheaper and more than 25% faster.File in questo prodotto:
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