A new, highly reconfigurable carry-skip adder for media signal processing is presented, The proposed circuit can be partitioned to perform one 64-, two 32-, four 16- and eight 8-bit additions. partitioning is obtained without increasing the critical path. When the AMS 0.35 mum two-poly three-metal 33 V CMOS (CSD) process the AMS 0.35 mum two-poly three-metal 33 V CMOS (CSD) process is used to produce the layout, the worst propagation delay and dissipation obtained is about 6.5 ns and 148 muW/MHz.
64-bit reconfigurable adder for low power media processing
PERRI, Stefania;CORSONELLO, Pasquale;COCORULLO, Giuseppe
2002-01-01
Abstract
A new, highly reconfigurable carry-skip adder for media signal processing is presented, The proposed circuit can be partitioned to perform one 64-, two 32-, four 16- and eight 8-bit additions. partitioning is obtained without increasing the critical path. When the AMS 0.35 mum two-poly three-metal 33 V CMOS (CSD) process the AMS 0.35 mum two-poly three-metal 33 V CMOS (CSD) process is used to produce the layout, the worst propagation delay and dissipation obtained is about 6.5 ns and 148 muW/MHz.File in questo prodotto:
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