New high performance circuit for statistical carry lookahead addition

This paper presents a new efficient VLSI implementation of a variable-time adder based on the statistical carry lookahead addition technique. As opposed to a previous proposal, the new circuit does not require precharged input signals. Therefore, it can be used in practical asynchronous system design and in mixed logic design without any auxiliary circuitry. For this reason, such implementation reduces power dissipation. The circuit is realized in domino logic and for the critical path DCVSL (differential cascode voltage switch logic) gates are used. A similar designed 56-bit adder requires 2758 transistors and shows an average delay of about 1.59 ns using MOSIS 0.5 mu m technology.