This paper presents an efficient and optimized carrier phase independent programmable Symbol Timing Recovery (STR) circuit. The novel structure is highly versatile. In fact, it can be configured at runtime to work in different conditions. All BPSK, QPSK and OQPSK modulations are supported thanks to runtime variable control coefficients. This approach also provides flexibility in performances and support for different sampling rates. The proposed circuit is presented in a Digital PLL loop structure and it is designed according to the Software Defined Radio (SDR) philosophy, which requires ever more flexible communication solutions able to support different protocols and standards. High performances are reached by the proposed hardware implementation, moreover, flexibility is guaranteed by the configurable architecture. When implemented with a Xilinx XC4VLX60 FPGA chip, the new circuit reaches the maximum running frequency of 108.7 MHz, thus sustaining a symbol rate of 10 MSps when 10 samples per symbol are employed. (C) 2008 Elsevier B.V. All rights reserved.

This paper presents an efficient and optimized carrier phase independent programmable Symbol Timing Recovery (STR) circuit. The novel structure is highly versatile. In fact, it can be configured at runtime to work in different conditions. All BPSK, QPSK and OQPSK modulations are supported thanks to runtime variable control coefficients. This approach also provides flexibility in performances and support for different sampling rates. The proposed circuit is presented in a Digital PLL loop structure and it is designed according to the Software Defined Radio (SDR) philosophy, which requires ever more flexible communication solutions able to support different protocols and standards. High performances are reached by the proposed hardware implementation, moreover, flexibility is guaranteed by the configurable architecture. When implemented with a Xilinx XC4VLX60 FPGA chip, the new circuit reaches the maximum running frequency of 108.7 MHz, thus sustaining a symbol rate of 10 MSps when 10 samples per symbol are employed. (C) 2008 Elsevier B.V. All rights reserved.

A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals

PERRI, Stefania;CORSONELLO, Pasquale
2008

Abstract

This paper presents an efficient and optimized carrier phase independent programmable Symbol Timing Recovery (STR) circuit. The novel structure is highly versatile. In fact, it can be configured at runtime to work in different conditions. All BPSK, QPSK and OQPSK modulations are supported thanks to runtime variable control coefficients. This approach also provides flexibility in performances and support for different sampling rates. The proposed circuit is presented in a Digital PLL loop structure and it is designed according to the Software Defined Radio (SDR) philosophy, which requires ever more flexible communication solutions able to support different protocols and standards. High performances are reached by the proposed hardware implementation, moreover, flexibility is guaranteed by the configurable architecture. When implemented with a Xilinx XC4VLX60 FPGA chip, the new circuit reaches the maximum running frequency of 108.7 MHz, thus sustaining a symbol rate of 10 MSps when 10 samples per symbol are employed. (C) 2008 Elsevier B.V. All rights reserved.
This paper presents an efficient and optimized carrier phase independent programmable Symbol Timing Recovery (STR) circuit. The novel structure is highly versatile. In fact, it can be configured at runtime to work in different conditions. All BPSK, QPSK and OQPSK modulations are supported thanks to runtime variable control coefficients. This approach also provides flexibility in performances and support for different sampling rates. The proposed circuit is presented in a Digital PLL loop structure and it is designed according to the Software Defined Radio (SDR) philosophy, which requires ever more flexible communication solutions able to support different protocols and standards. High performances are reached by the proposed hardware implementation, moreover, flexibility is guaranteed by the configurable architecture. When implemented with a Xilinx XC4VLX60 FPGA chip, the new circuit reaches the maximum running frequency of 108.7 MHz, thus sustaining a symbol rate of 10 MSps when 10 samples per symbol are employed. (C) 2008 Elsevier B.V. All rights reserved.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/128116
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