A Matrix Product Accelerator for Field Programmable Systems on Chip

This paper presents a novel architecture for matrix multiplication optimized to be integrated as a coprocessor unit with embedded processors in modern FPGAs. In contrast with previous proposals that accelerate just the matrix multiplication computation, the coprocessor here proposed has been purposely designed to exploit an efficient communication protocol for the data exchange between it and the host processor that significantly reduces the whole computational time. The complete system formed by a 32-bit RISC processor augmented by the proposed coprocessor unit has been hardware implemented. Such system can be easily used to accelerate matrix multiplication with virtually any matrix sizes. Simulation tests and measurements demonstrate that the system requires a number of clock cycles more than halved, with respect to competitive solutions.

This paper presents a novel architecture for matrix multiplication optimized to be integrated as a coprocessor unit with embedded processors in modern FPGAs. In contrast with previous proposals that accelerate just the matrix multiplication computation, the coprocessor here proposed has been purposely designed to exploit an efficient communication protocol for the data exchange between it and the host processor that significantly reduces the whole computational time. The complete system formed by a 32-bit RISC processor augmented by the proposed coprocessor unit has been hardware implemented. Such system can be easily used to accelerate matrix multiplication with virtually any matrix sizes. Simulation tests and measurements demonstrate that the system requires a number of clock cycles more than halved, with respect to competitive solutions. (c) 2007 Elsevier B.V. All rights reserved.