This paper presents a microprocessor-based FPGA system for lossy image compression. The system implements a widely known wavelet-based compression method, i.e. the Set Partitioning In Hierarchical Trees algorithm (SPIHT). The computationally intensive 2D wavelet-transform is performed by means of custom circuits, whereas an embedded microprocessor is used to execute a purpose-build SPIHT encoding process. The aim of this work is to demonstrate and verify the feasibility of a compact and programmable image compression sub-system that uses just one low-cost FPGA device. The entire system consumes just 1637 slices of an XC2V chip, it runs at 100 MHz clock frequency and reaches a speed performance suitable for several real-time applications. (C) 2004 Elsevier B.V. All rights reserved.

Microprocessor-based FPGA implementation of SPIHT image compression subsystems

CORSONELLO, Pasquale;PERRI, Stefania;COCORULLO, Giuseppe
2005

Abstract

This paper presents a microprocessor-based FPGA system for lossy image compression. The system implements a widely known wavelet-based compression method, i.e. the Set Partitioning In Hierarchical Trees algorithm (SPIHT). The computationally intensive 2D wavelet-transform is performed by means of custom circuits, whereas an embedded microprocessor is used to execute a purpose-build SPIHT encoding process. The aim of this work is to demonstrate and verify the feasibility of a compact and programmable image compression sub-system that uses just one low-cost FPGA device. The entire system consumes just 1637 slices of an XC2V chip, it runs at 100 MHz clock frequency and reaches a speed performance suitable for several real-time applications. (C) 2004 Elsevier B.V. All rights reserved.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/135985
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