An automated system, designed to perform innovative reliability tests on semiconductor power devices, is reported. Hardware and software modules have been specifically developed for the demonstration of the proposed methodology. Both High Temperature Reverse Bias (HTRB) and Electrical Characterization Test (ECT) are executed by the system on power transistors, increasing operation parameters beyond their rated temperature and voltage values in order to accelerate the device wearing out. Thanks to a purposely designed mini heater, the system tightly controls the individual chip temperature, while allowing the testing of many devices at a time. Electrical parameters can be periodically measured in order to determine early warnings of device failure, being able to stop their stress, both thermal and electrical, avoiding uncontrolled thermal runaway effects that often lead to package explosion. This strategy, on one hand, can avoid interruption of the remaining device test and, on the other hand, make it possible to perform, after the test end, the most complete post failure analysis. A non standard procedure for HTRB tests, based on the division of the total stress time in several short periods, is proposed.
Instrumentation for Innovative Semiconductor Power Devices Reliability Tests
PACE, Calogero;
2013-01-01
Abstract
An automated system, designed to perform innovative reliability tests on semiconductor power devices, is reported. Hardware and software modules have been specifically developed for the demonstration of the proposed methodology. Both High Temperature Reverse Bias (HTRB) and Electrical Characterization Test (ECT) are executed by the system on power transistors, increasing operation parameters beyond their rated temperature and voltage values in order to accelerate the device wearing out. Thanks to a purposely designed mini heater, the system tightly controls the individual chip temperature, while allowing the testing of many devices at a time. Electrical parameters can be periodically measured in order to determine early warnings of device failure, being able to stop their stress, both thermal and electrical, avoiding uncontrolled thermal runaway effects that often lead to package explosion. This strategy, on one hand, can avoid interruption of the remaining device test and, on the other hand, make it possible to perform, after the test end, the most complete post failure analysis. A non standard procedure for HTRB tests, based on the division of the total stress time in several short periods, is proposed.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
