New methodology for the design of efficient binary addition circuits in QCA

The QCA approach is an attractive emerging technology suitable for the development of ultra-dense low-power high-performance digital circuits. Even though several solutions have been proposed recently for binary addition circuits, the design of efficient adders in QCA still poses several challenges since, most often, designers tend to implement strategies and methodologies close to those consolidated for the CMOS logic design. In this paper, we propose a new design method that exploits in original ways the properties of auxiliary propagate and generate signals to reduce the number of Majority Gates required to implement adders in QCA and/or the addition time. Three new formulations of basic logic equations frequently used in the designs of fast binary adders are proposed. To evaluate the potential advantage of the new strategy, two examples of application of the above method are discussed in the paper.