A new high-performance variable time adder is presented which is based on the statistical carry look-ahead addition technique. The new circuit uses carry-select stages to reduce the critical path. A 56 bit adder designed for and realised using 0.5 mu m CMOS technology shows an average addition time of similar to 1.28 ns.
Hybrid carry-select statistical carry look-ahead adder
CORSONELLO, Pasquale;PERRI, Stefania;Cocorullo G.
1999-01-01
Abstract
A new high-performance variable time adder is presented which is based on the statistical carry look-ahead addition technique. The new circuit uses carry-select stages to reduce the critical path. A 56 bit adder designed for and realised using 0.5 mu m CMOS technology shows an average addition time of similar to 1.28 ns.File in questo prodotto:
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