This paper presents a novel technique to design fast-squaring circuits. The proposed approach speeds up squaring operations combining the 3-bit scan without overlapping bits and the folding technique. Several hardware implementations of squarer circuits designed as described here are characterized for several operand wordlengths. Obtained results demonstrate that, using the ST 90 nm 1V CMOS technology, a 32-bit squarer exploiting the novel way of generating partial products reaches a 769MHz running frequency, dissipates less than 19.3mW on average and occupies similar to 91000 mu m(2) of silicon area. Copyright (C) 2010 John Wiley & Sons, Ltd.

This paper presents a novel technique to design fast-squaring circuits. The proposed approach speeds up squaring operations combining the 3-bit scan without overlapping bits and the folding technique. Several hardware implementations of squarer circuits designed as described here are characterized for several operand wordlengths. Obtained results demonstrate that, using the ST 90 nm 1V CMOS technology, a 32-bit squarer exploiting the novel way of generating partial products reaches a 769MHz running frequency, dissipates less than 19.3mW on average and occupies similar to 91000 mu m(2) of silicon area. Copyright (C) 2010 John Wiley & Sons, Ltd.

Fast-squarer circuits using 3-bit-scan without overlapping bits

PERRI, Stefania;CORSONELLO, Pasquale
2011

Abstract

This paper presents a novel technique to design fast-squaring circuits. The proposed approach speeds up squaring operations combining the 3-bit scan without overlapping bits and the folding technique. Several hardware implementations of squarer circuits designed as described here are characterized for several operand wordlengths. Obtained results demonstrate that, using the ST 90 nm 1V CMOS technology, a 32-bit squarer exploiting the novel way of generating partial products reaches a 769MHz running frequency, dissipates less than 19.3mW on average and occupies similar to 91000 mu m(2) of silicon area. Copyright (C) 2010 John Wiley & Sons, Ltd.
This paper presents a novel technique to design fast-squaring circuits. The proposed approach speeds up squaring operations combining the 3-bit scan without overlapping bits and the folding technique. Several hardware implementations of squarer circuits designed as described here are characterized for several operand wordlengths. Obtained results demonstrate that, using the ST 90 nm 1V CMOS technology, a 32-bit squarer exploiting the novel way of generating partial products reaches a 769MHz running frequency, dissipates less than 19.3mW on average and occupies similar to 91000 mu m(2) of silicon area. Copyright (C) 2010 John Wiley & Sons, Ltd.
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/142443
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 1
  • ???jsp.display-item.citation.isi??? 0
social impact