A new VLSI 3:1 multiplexer is presented. The proposed circuit is based on a double controlled tri-state buffer. A custom cell which can easily be added to the AMS 0.6 mum CMOS standard cell library has been developed. The new cell shows a propagation delay of similar to 780ps and dissipates 5.2 muW/MHz.
Design of 3 : 1 multiplexer standard cell
CORSONELLO, Pasquale;PERRI, Stefania;
2000
Abstract
A new VLSI 3:1 multiplexer is presented. The proposed circuit is based on a double controlled tri-state buffer. A custom cell which can easily be added to the AMS 0.6 mum CMOS standard cell library has been developed. The new cell shows a propagation delay of similar to 780ps and dissipates 5.2 muW/MHz.File in questo prodotto:
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