CINECA IRIS Institutional Research Information System
IRIS è la soluzione IT che facilita la raccolta e la gestione dei dati relativi alle attività e ai prodotti della ricerca. Fornisce a ricercatori, amministratori e valutatori gli strumenti per monitorare i risultati della ricerca, aumentarne la visibilità e allocare in modo efficace le risorse disponibili.
EnglishThis paper presents a new efficient architecture for the design of fast low-cost single-clock-cycle binary comparators. The proposed 64-bit circuit requires only 1051 transistors and, when implemented by using the ST 90-nm 1-V CMOS technology, it exhibits a running frequency higher than 4 GHz with an average power dissipation of only similar to 4 mW. Comparison with the fastest comparator known in the literature demonstrates that, at a parity of technology used, the novel architecture is similar to 12% faster and requires similar to 69% less transistors.
This paper presents a new efficient architecture for the design of fast low-cost single-clock-cycle binary comparators. The proposed 64-bit circuit requires only 1051 transistors and, when implemented by using the ST 90-nm 1-V CMOS technology, it exhibits a running frequency higher than 4 GHz with an average power dissipation of only similar to 4 mW. Comparison with the fastest comparator known in the literature demonstrates that, at a parity of technology used, the novel architecture is similar to 12% faster and requires similar to 69% less transistors.
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator / Perri, Stefania; Corsonello, Pasquale. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - 55:12(2008), pp. 1239-1243.
Scheda prodotto non validato
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo
| Titolo: | Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator |
| Autori: | |
| Data di pubblicazione: | 2008 |
| Rivista: | |
| Citazione: | Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator / Perri, Stefania; Corsonello, Pasquale. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - 55:12(2008), pp. 1239-1243. |
| Handle: | http://hdl.handle.net/20.500.11770/142494 |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
File in questo prodotto:
http://hdl.handle.net/20.500.11770/142494
Copyright © 2021