A new highly reconfigurable Manchester adder for low-power media signal processing is presented. The proposed circuit can be run-time partitioned. Its 64-bit version performs one 64-, two 32-, four 16-, or eight 8-bit additions. When the AMS 0.35mm 2-poly 3-metal 3.3V CMOS (CSD) process is used to produce a layout, an energy dissipation of only 78 pJ and a worst propagation delay of about 10.2 ns are obtained. The novelty demonstrated in this letter is that the introduction of dummy bit positions along the carry-path can be avoided using on-purpose dynamic logic stages.
Efficient reconfigurable Manchester adders for low-power media processing
CORSONELLO, Pasquale;PERRI, Stefania
2005-01-01
Abstract
A new highly reconfigurable Manchester adder for low-power media signal processing is presented. The proposed circuit can be run-time partitioned. Its 64-bit version performs one 64-, two 32-, four 16-, or eight 8-bit additions. When the AMS 0.35mm 2-poly 3-metal 3.3V CMOS (CSD) process is used to produce a layout, an energy dissipation of only 78 pJ and a worst propagation delay of about 10.2 ns are obtained. The novelty demonstrated in this letter is that the introduction of dummy bit positions along the carry-path can be avoided using on-purpose dynamic logic stages.File in questo prodotto:
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