In this paper we describe an analytical model for the gate current 1/f noise in a MOS device. The model is based on a simple idea: one electron trapped in the dielectric switches-off tunneling through the oxide over an equivalent blocking area. The effective trap density inside the dielectric can be extracted as a function of energy from gate current noise measurements. The Gate Noise Parameter (GNP) is introduced as a new figure of merit for the quality of the gate stack. The GNP can be related to physical quantities of the MOS structure on the basis of the proposed model.

A model for MOS gate stack quality evaluation based on the gate current 1/f noise

CRUPI, Felice;PACE, Calogero;
2008-01-01

Abstract

In this paper we describe an analytical model for the gate current 1/f noise in a MOS device. The model is based on a simple idea: one electron trapped in the dielectric switches-off tunneling through the oxide over an equivalent blocking area. The effective trap density inside the dielectric can be extracted as a function of energy from gate current noise measurements. The Gate Noise Parameter (GNP) is introduced as a new figure of merit for the quality of the gate stack. The GNP can be related to physical quantities of the MOS structure on the basis of the proposed model.
2008
978-142441730-8
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/160923
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