A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption

Static energy consumption due to subthreshold leakage current is an overriding problem in SRAM structures such as on chip cache memories. To overcome this challenge, several techniques limiting the subthreshold current in a SRAM cell have been proposed. They limit the subthreshold current in a SRAM cell but they also cause an increase in dynamic energy during the cell access operation. In this paper the actual energy saving offered by these techniques in the context of a microprocessor memory hierarchy consisting of two cache levels is examined. A new SRAM scheme is also proposed which does not introduce time and energy penalties with respect to the conventional 6T cell. Simulations based on UMC 0.18um-1.8V and ST 90nm-1V process models demonstrate that the conventional low-leakage techniques save a significant amount of leakage energy but they also increase the dynamic energy dissipation and the access delay. By using the technique proposed here the static energy dissipation is reduced up to 42% with respect to the 6T cell without increasing the dynamic energy dissipation or the cell access delay.