FRUSTACI, Fabio

FRUSTACI, Fabio  

Dipartimento di Ingegneria Informatica, Modellistica, Elettronica e Sistemistica  

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Risultati 1 - 20 di 69 (tempo di esecuzione: 0.022 secondi).
Titolo Data di pubblicazione Autore(i) File
A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS 1-gen-2014 Frustaci, F.; Khayatzadeh, M.; Blaauw, D.; Sylvester, D.; Alioto, M.
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 1-gen-2020 Spagnolo, F.; Frustaci, F.; Perri, S.; Corsonello, P.
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 1-gen-2022 Frustaci, Fabio; Spagnolo, Fanny; Perri, Stefania; Corsonello, Pasquale
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 1-gen-2015 Corsonello, Pasquale; Frustaci, F; Perri, Stefania
A low-leakage single ended 6T SRAM cell 1-gen-2010 Solanki, S.; Frustaci, F.; Corsonello, Pasquale
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 1-gen-2009 Frustaci, F; Corsonello, Pasquale; Perri, S; Cocorullo, Giuseppe
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 1-gen-2009 Frustaci, F.; Corsonello, Pasquale; Perri, Stefania; Cocorullo, G.
A new low-power high-speed single-clock-cycle binary comparator 1-gen-2010 Frustaci, F.; Perri, Stefania; Lanuzza, Marco; Corsonello, Pasquale
A new noise-tolerant dynamic logic circuit design 1-gen-2007 Frustaci, F; Corsonello, Pasquale; Cocorullo, Giuseppe
A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder 1-gen-2010 Frustaci, F; Lanuzza, Marco
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 1-gen-2006 Frustaci F; Corsonello P; Perri S; Cocorullo G
A novel background subtraction method based on color invariants and grayscale levels 1-gen-2014 Guachi, L; Cocorullo, Giuseppe; Corsonello, Pasquale; Frustaci, F; Perri, Stefania
A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS 1-gen-2015 Khayatzadeh, M.; Frustaci, F.; Blaauw, D.; Sylvester, D.; Alioto, M.
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 1-gen-2010 Lanuzza, Marco; Zicari, P; Perri, Stefania; Frustaci, F; Corsonello, Pasquale
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 1-gen-2021 Perri, S.; Spagnolo, F.; Frustaci, F.; Corsonello, P.
Accurate power estimation model for CMOS adders optimization 1-gen-2004 Perri, Stefania; Frustaci, F; Corsonello, Pasquale
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 1-gen-2009 Lanuzza, Marco; Zicari, P; Frustaci, F; Perri, Stefania; Corsonello, Pasquale
An efficient connected component labeling architecture for embedded systems 1-gen-2018 Spagnolo, F.; Frustaci, F.; Perri, S.; Corsonello, P.
An Efficient Hardware-Oriented Stereo Matching Algorithm 1-gen-2016 Cocorullo, G; Corsonello, Pasquale; Frustaci, F; Perri, Stefania
An embedded machine vision system for an in-line quality check of assembly processes 1-gen-2020 Frustaci, Fabio; Perri, Stefania; Cocorullo, Giuseppe; Corsonello, Pasquale