Self-Repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology

With aggressive scaling, one of the major barriers that CMOS technology faces is the increasing process variations. The variations in process parameters not only affect the performance of the devices but also degrade the parametric yield of the circuits. Adaptive repairing techniques like adaptive body bias were proved to be effective to mitigate variations in the process parameters. In this paper, we evaluate the use of zone based self-repairing techniques to mitigate the impact of process variations on SRAM cells. Two different techniques were experimented and analyzed through extensive Monte Carlo simulations and exploiting a commercial 65nm technology. Obtained results demonstrate that improvements up to 35.7% in variability factor for leakage power and up to 22.3% in Design Margin for leakage power can be achieved by using the suggested approach.