IRIS

LANUZZA, Marco

LANUZZA, Marco  

Dipartimento di Ingegneria Informatica, Modellistica, Elettronica e Sistemistica  

Mostra records
Risultati 1 - 20 di 152 (tempo di esecuzione: 0.033 secondi).
Titolo Data di pubblicazione Autore(i) File
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS 1-gen-2022 Zambrano, Benjamin; Garzon, Esteban; Strangio, S.; Crupi, F.; Lanuzza, M.
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 1-gen-2020 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 1-gen-2021 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
A 0.6V–1.8V Compact Temperature Sensor with 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06 nJ per Conversion 1-gen-2022 Zambrano, Benjamin.; Garzon, Esteban; Strangio, S.; Iannaccone, G.; Lanuzza, M.
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET 1-gen-2020 Shavit, N.; Stanger, I.; Taco, R.; Lanuzza, M.; Fish, A.
A 180 nm Low-Cost Operational Amplifier for IoT Applications 1-gen-2021 Vicuna, K.; Mosquera, C.; Rendon, M.; Musello, A.; Lanuzza, M.; Procel, L. M.; Taco, R.; Trojman, L.
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 1-gen-2021 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs 1-gen-2017 De Rose, Raffaele; Lanuzza, Marco; D'Aquino, Massimiliano; Carangelo, Greta; Finocchio, Giovanni; Crupi, Felice; Carpentieri, Mario
A comparative study of MWT architectures by means of numerical simulations 1-gen-2013 Magnone, P.; Tonini, D.; De Rose, R.; Frei, M.; Crupi, F.; Lanuzza, M.; Sangiorgi, E.; Fiegna, C.
A high-performance fully reconfigurable FPGA-based 2D convolution processor 1-gen-2005 Perri, Stefania; Lanuzza, Marco; Corsonello, Pasquale; Cocorullo, Giuseppe
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory 1-gen-2023 Garzon, E.; Golman, R.; Lanuzza, M.; Teman, A.; Yavits, L.
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation 1-gen-2023 Garzon, E.; Yavits, L.; Finocchio, G.; Carpentieri, M.; Teman, A.; Lanuzza, M.
A low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks 1-gen-2021 Vatalaro, M.; Lanuzza, M.; Crupi, F.; Moposita, T.; Trojman, L.; Vladimirescu, A.; Strangio, S.
A new low-power high-speed single-clock-cycle binary comparator 1-gen-2010 Frustaci, F.; Perri, Stefania; Lanuzza, Marco; Corsonello, Pasquale
A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder 1-gen-2010 Frustaci, F; Lanuzza, Marco
A new reconfigurable coarse-grain architecture for multimedia applications 1-gen-2007 Lanuzza, Marco; Perri, Stefania; Corsonello, Pasquale; Margala, M.
A novel ICA-based hardware system for reconfigurable and portable BCI 1-gen-2009 Palumbo, A; Calabrese, B; Cocorullo, Giuseppe; Lanuzza, Marco; Veltri, P; Vizza, P; Gambardella, A; Sturniolo, M.
A Physical Unclonable Function Based on a 2-Transistor Subthreshold Voltage Divider 1-gen-2017 De Rose, R; Crupi, Felice; Lanuzza, Marco; Albano, D.
A portable class of 3-transistor current references with low-power sub-0.5 V operation 1-gen-2018 Crupi, Felice; De Rose, Raffaele; Paliy, Maksym; Lanuzza, Marco; Perna, Mattia; Iannaccone, Giuseppe
A RISC-V-based Research Platform for Rapid Design Cycle 1-gen-2022 Garzon, Esteban; Golman, Roman; Harel, Odem; Noy, Tzachia; Kra, Yehuda; Pollock, Asaf; Yuzhaninov, Slava; Shoshan, Yonatan; Rudin, Yehuda; Weitzman, Yoav; Lanuzza, Marco; Teman, Adam