LANUZZA, Marco

LANUZZA, Marco  

Dipartimento di Ingegneria Informatica, Modellistica, Elettronica e Sistemistica  

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Risultati 1 - 20 di 129 (tempo di esecuzione: 0.025 secondi).
Titolo Data di pubblicazione Autore(i) File
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS 1-gen-2022 Zambrano, B.; Garzon, E.; Strangio, S.; Crupi, F.; Lanuzza, M.
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 1-gen-2020 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 1-gen-2021 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
A 0.6V–1.8V Compact Temperature Sensor with 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06 nJ per Conversion 1-gen-2022 Zambrano, B.; Garzon, E.; Strangio, S.; Iannaccone, G.; Lanuzza, M.
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET 1-gen-2020 Shavit, N.; Stanger, I.; Taco, R.; Lanuzza, M.; Fish, A.
A 180 nm Low-Cost Operational Amplifier for IoT Applications 1-gen-2021 Vicuna, K.; Mosquera, C.; Rendon, M.; Musello, A.; Lanuzza, M.; Procel, L. M.; Taco, R.; Trojman, L.
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 1-gen-2021 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI 1-gen-2019 Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs 1-gen-2022 Garzon, E.; De Rose, R.; Crupi, F.; Trojman, L.; Teman, A.; Lanuzza, M.
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 1-gen-2014 Frustaci, Fabio; Lanuzza, Marco; Perri, Stefania; Corsonello, Pasquale
Assessment of 2D-FET Based Digital and Analog Circuits on Paper 1-gen-2021 Vatalaro, M.; De Rose, R.; Lanuzza, M.; Iannaccone, G.; Crupi, F.
Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits 1-gen-2016 Strangio, S; Palestri, P; Lanuzza, Marco; Crupi, Felice; Esseni, D; Selmi, L.
Assessment of paper-based MoS2 FET for Physically Unclonable Functions 1-gen-2022 Vatalaro, M.; De Rose, R.; Lanuzza, M.; Magnone, P.; Conti, S.; Iannaccone, G.; Crupi, F.
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 1-gen-2019 Garzon, E.; De Rose, R.; Crupi, F.; Trojman, L.; Lanuzza, M.
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 1-gen-2020 Garzon, E.; De Rose, R.; Crupi, F.; Trojman, L.; Finocchio, G.; Carpentieri, M.; Lanuzza, M.
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmentic circuits 1-gen-2017 Strangio, S; Palestri, P; Lanuzza, M; Esseni, D; Crupi, Felice; Selmi, L.
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits 1-gen-2017 Strangio, S; Palestri, P; Lanuzza, Marco; Esseni, D; Crupi, F; Selmi, L.
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders 1-gen-2016 Strangio, S; Palestri, P; Lanuzza, Marco; Crupi, Felice; Esseni, D; Selmi, L.
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs 1-gen-2017 De Rose, Raffaele; Lanuzza, Marco; D'Aquino, Massimiliano; Carangelo, Greta; Finocchio, Giovanni; Crupi, Felice; Carpentieri, Mario
Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers 1-gen-2019 De Rose, R.; D'Aquino, M.; Finocchio, G.; Crupi, F.; Carpentieri, M.; Lanuzza, M.