Self-timed adders are today widely used since they compute in mean time. Traditionally, in order to achieve very high-speed performance they are realized using dynamic CMOS logic (Domino, DCVSL). However, recent works have demonstrated that eficient self-timed adders can also be realized using fully static CMOS circuits. In this paper a new high-performance,fully static 54-bit self-timed adder is presented. The proposed VLSI implementation uses overlapped execution circuits, which perform their computation exploiting the initialization time elapsing between two consecutive operations. The new adder realized with AMS 0.6 μm CMOS standard-cells shows an average addition time of ∼3.3ns, requires ∼900000μm2 of silicon area and consumes a maximum power of ∼660mW@300MHz.
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits
PERRI, Stefania;CORSONELLO, Pasquale;COCORULLO, Giuseppe;CAPPUCCINO, Gregorio;
2001-01-01
Abstract
Self-timed adders are today widely used since they compute in mean time. Traditionally, in order to achieve very high-speed performance they are realized using dynamic CMOS logic (Domino, DCVSL). However, recent works have demonstrated that eficient self-timed adders can also be realized using fully static CMOS circuits. In this paper a new high-performance,fully static 54-bit self-timed adder is presented. The proposed VLSI implementation uses overlapped execution circuits, which perform their computation exploiting the initialization time elapsing between two consecutive operations. The new adder realized with AMS 0.6 μm CMOS standard-cells shows an average addition time of ∼3.3ns, requires ∼900000μm2 of silicon area and consumes a maximum power of ∼660mW@300MHz.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
