In this paper, the architecture of a novel reconfigurable array,optimized for high-throughput and low-power Digital Signal Processing, is described.The proposed reconfigurable system consists of 2D array of homogeneouscoarse-grain reconfigurable cells organized into a hierarchical two-levelarchitecture. The system has been characterized for performing different DSPtasks. Comparison results demonstrate speedups up to 8X with energy efficiencyimprovement up to 58% over a state of the art FPGA.
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing
Lanuzza M;PERRI, Stefania;CORSONELLO, Pasquale
2009-01-01
Abstract
In this paper, the architecture of a novel reconfigurable array,optimized for high-throughput and low-power Digital Signal Processing, is described.The proposed reconfigurable system consists of 2D array of homogeneouscoarse-grain reconfigurable cells organized into a hierarchical two-levelarchitecture. The system has been characterized for performing different DSPtasks. Comparison results demonstrate speedups up to 8X with energy efficiencyimprovement up to 58% over a state of the art FPGA.File in questo prodotto:
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