A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation

Dynamic CMOS gates are widely used in high performance circuits even though they are less noise tolerant than their static CMOS counterparts. In the literature, several techniques are known that enhance the noise-tolerance but sacrifice speed performances and energy dissipation. This paper presents a new technique for increasing the noise tolerance of dynamic CMOS gate minimizing speed and energy penalties. A wide comparison with previous techniques has been carried out. When the STMicroelectronics CMOS 90nm-1V technology is used, the proposed design technique exhibits the highest level of noise robustness (718mV). Moreover, at a parity of the noise-robustness, it achieves an energy- delay product (EDP) up to 54% lower than previous proposals.