This work proposes an area-efficient approach to fully exploit redundancy in reconfigurable sense amplifiers (SAs). The proposed SA can combine/invert offsets of sub-unit SAs, reducing offset by up to 3.1x at iso-area in 28nm FDSOI.
A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS
Frustaci F.
;Alioto M.
2015-01-01
Abstract
This work proposes an area-efficient approach to fully exploit redundancy in reconfigurable sense amplifiers (SAs). The proposed SA can combine/invert offsets of sub-unit SAs, reducing offset by up to 3.1x at iso-area in 28nm FDSOI.File in questo prodotto:
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