Design and analysis of a leading one detector-based approximate multiplier on FPGA

In the context of error-tolerant applications, several approximate multipliers have been proposed to trade the energy consumption with the result accuracy. Unlikely, most of them are conceived for Application Specific Integrated Circuits and they can not be implemented on Field Programmable Gate Arrays due to their unique hardware structure. Among the others, the Leading One Detector-based approximate multipliers have attracted a lot of interest due to their efficiency. Nevertheless, a complete characterization of this kind of multipliers on Field Programmable Gate Arrays is still missing. This paper presents a thorough analysis of the approximate multiplier known as Dynamic Range Unbiased Multiplier when implemented on Field Programmable Gate Arrays, and it provides useful design guidelines to get the optimum energy-quality trade-off. Moreover, a simple approximation strategy is proposed to further increase the multiplier efficiency, leading to an energy reduction of up to 34% and a quality increase of up to 43% with respect to the conventional structure. Finally, the possibility of enhancing the referred approximate multiplier with a dynamically tuning of the energy-quality trade-off is analysed.