This paper presents a multi-exposure fusion approach suitable to be hardware implemented and integrated in real-time video processing pipelines. The proposed approach is inspired by the Merten's algorithm for blending images in a multi-exposure sequence through simple quality measures, such as saturation and contrast. However, for the purpose of a hardware-friendly implementation, complex Laplacian and Gaussian pyramid computations are here replaced with simpler operations. The proposed approach is suitable to be integrated within a complete system targeting heterogeneous FPGA SoCs. When implemented within the Xilinx Zynq XC7Z020 chip, it runs 94 Mega pixels per second and occupies just 18493 LUTs, which is at least 25% faster and 35.5% cheaper than state-of-the-art designs.
Hardware-Oriented Multi-Exposure Fusion Approach for Real-Time Video Processing on FPGA
Sangiovanni M. A.;Spagnolo F.;Corsonello P.
2022-01-01
Abstract
This paper presents a multi-exposure fusion approach suitable to be hardware implemented and integrated in real-time video processing pipelines. The proposed approach is inspired by the Merten's algorithm for blending images in a multi-exposure sequence through simple quality measures, such as saturation and contrast. However, for the purpose of a hardware-friendly implementation, complex Laplacian and Gaussian pyramid computations are here replaced with simpler operations. The proposed approach is suitable to be integrated within a complete system targeting heterogeneous FPGA SoCs. When implemented within the Xilinx Zynq XC7Z020 chip, it runs 94 Mega pixels per second and occupies just 18493 LUTs, which is at least 25% faster and 35.5% cheaper than state-of-the-art designs.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
