This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuit-level, benchmarking TFET - against FinFET-based bitcells focusing on their write operation. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies in a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.
Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells
Taco Ramiro.;
2022-01-01
Abstract
This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuit-level, benchmarking TFET - against FinFET-based bitcells focusing on their write operation. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies in a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.File in questo prodotto:
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