TACO LASSO, Edison Ramiro

TACO LASSO, Edison Ramiro  

Dipartimento di Ingegneria Informatica, Modellistica, Elettronica e Sistemistica  

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Risultati 1 - 20 di 28 (tempo di esecuzione: 0.075 secondi).
Titolo Data di pubblicazione Autore(i) File
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET 1-gen-2020 Shavit, N.; Stanger, I.; Taco, R.; Lanuzza, M.; Fish, A.
A 180 nm Low-Cost Operational Amplifier for IoT Applications 1-gen-2021 Vicuna, K.; Mosquera, C.; Rendon, M.; Musello, A.; Lanuzza, M.; Procel, L. M.; Taco, R.; Trojman, L.
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI 1-gen-2019 Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander
Dynamic gate-level body biasing for subthreshold digital design 1-gen-2014 Lanuzza, Marco; Taco, R; Albano, D.
Energy efficient self-adaptive dual mode logic address decoder 1-gen-2021 Vicuna, K.; Mosquera, C.; Musello, A.; Benedictis, S.; Rendon, M.; Garzon, Esteban; Procel, L. M.; Trojman, L.; Taco, R.
Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI 1-gen-2017 Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander
Evaluation of Dual Mode Logic in 28nm FD-SOI technology 1-gen-2017 Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander
Exploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology 1-gen-2020 Taco, R.; Yavits, L.; Shavit, N.; Stanger, I.; Lanuzza, M.; Fish, A.
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design 1-gen-2014 Taco, R; Levi, I; Fish, A; Lanuzza, Marco
Extended Exploration of Low Granularity Back Biasing Control in 28nm UTBB FD-SOI Technology 1-gen-2016 Taco, R; Levi, I; Lanuzza, Marco; Fish, A.
FlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic 1-gen-2023 Stanger, I.; Shavit, N.; Taco, R.; Lanuzza, M.; Yavits, L.; Levi, I.; Fish, A.
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines 1-gen-2015 Albano, D; Lanuzza, Marco; Taco, R; Crupi, Felice
High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator 1-gen-2021 Escobar, R.; Procel, L. M.; Trojman, L.; Lanuzza, M.; Taco, R.
Improving speed and power characteristics of pulse-triggered flip-flops 1-gen-2014 Lanuzza, Marco; Taco, R.
Live demo: An 88FJ / 40 MHz [0.4V] - 0.61PJ / 1GHz [0.9V] dual mode logic 8x8-bit multiplier accumulator with a self-adjustment mechanism in 28 nm FD-SOI 1-gen-2019 Taco, R.; Levi, I.; Lanuzza, M.; Fish, A.
Live Demo: Silicon evaluation of multimode dual mode logic for PVT-aware datapaths 1-gen-2021 Stanger, I.; Shavit, N.; Taco, R.; Lanuzza, M.; Fish, A.
Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET 1-gen-2021 Shavit, N.; Stanger, I.; Taco, R.; Lanuzza, M.; Fish, A.
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI 1-gen-2016 Taco, R; Levi, I; Lanuzza, Marco; Fish, A.
Low voltage Ripple Carry Adder with low-Granularity Dynamic Forward Back-Biasing in 28 nm UTBB FD-SOI 1-gen-2015 Taco, R; Levi, I; Lanuzza, Marco; Fish, A.
Performance Benchmarking of TFET and FinFET Digital Circuits from a Synthesis-Based Perspective 1-gen-2022 Rendon, M.; Cao, C.; Landazuri, K.; Garzon, Esteban; Procel, L. M.; Taco, R.