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TACO LASSO, Edison Ramiro

TACO LASSO, Edison Ramiro  

Dipartimento di Ingegneria Informatica, Modellistica, Elettronica e Sistemistica  

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Risultati 1 - 20 di 51 (tempo di esecuzione: 0.007 secondi).
Titolo Data di pubblicazione Autore(i) File
720p-HD Gray-scale and Color Images Shape Recognition System Implementation on an FPGA Platform with a 1080pFull-HD HDMI Interface using a Hu Moments Algorithm 1-gen-2020 Borja, A.; Toscano, F.; Cardenas, D.; Ramiro, Taco; Trojman, L.; Procel, L. -M.
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET 1-gen-2020 Shavit, N.; Stanger, I.; Taco, R.; Lanuzza, M.; Fish, A.
A 180 nm Low-Cost Operational Amplifier for IoT Applications 1-gen-2021 Vicuna, K.; Mosquera, C.; Rendon, M.; Musello, A.; Lanuzza, M.; Procel, L. M.; Taco, R.; Trojman, L.
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic 1-gen-2022 Shifman, Yizhak; Stanger, Inbal; Shavit, Netanel; Taco, Ramiro; Fish, Alexander; Shor, Joseph
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI 1-gen-2019 Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander
Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits 1-gen-2021 Rendon, M.; Cao, C.; Landazuri, K.; Procel, L. M.; Trojman, L.; Ramiro, Taco
Assessment of a universal logic gate and a full adder circuit based on CMOS-memristor technology 1-gen-2023 Guitarra, S.; Taco, Ramiro.; Gavilanez, M.; Yepez, J.; Espinoza, U.
Design of an Air Pollution Monitoring System Based on a Low-Cost Sensor Node 1-gen-2024 Guerron, R. -A.; Carni, D. -L.; Lanuzza, M.; D'Amore, F.; Bencardino, M.; Lamonaca, F.; Taco, R.
Designing Precharge-Free Energy-Efficient Content-Addressable Memories 1-gen-2024 Taco, Ramiro; Garzón, Esteban; Hanhan, Robert; Teman, Adam; Yavits, Leonid; Lanuzza, Marco
DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems 1-gen-2022 Vicuna, Kevin; Procel, Luis-Miguel; Trojman, Lionel; Taco, Ramiro
Dual mode logic address decoder 1-gen-2020 Yavits, L.; Taco, Ramiro.; Shavit, N.; Stanger, I.; Fish, A.
Dynamic gate-level body biasing for subthreshold digital design 1-gen-2014 Lanuzza, Marco; Taco, R; Albano, D.
Effects of the technology scaling down to 28nm on Ultra-Low Voltage and Power OTA performance using TCAD simulations 1-gen-2020 Trojman, L.; Orozco, J.; Bonilla, M.; Valencia, M.; Borja, A.; Procel, L. M.; Taco, Ramiro.
Efficiency of Dual Mode Logic in Nanoscale Technology Nodes 1-gen-2018 Shavit, N.; Taco, Ramiro.; Fish, A.
Energy efficient self-adaptive dual mode logic address decoder 1-gen-2021 Vicuna, K.; Mosquera, C.; Musello, A.; Benedictis, S.; Rendon, M.; Garzon, Esteban; Procel, L. M.; Trojman, L.; Taco, R.
Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI 1-gen-2017 Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander
Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells 1-gen-2022 Musello, A.; Perez, S. S.; Villegas, M.; Procel, L. M.; Taco, Ramiro.; Trojman, L.
Evaluation of Dual Mode Logic in 28nm FD-SOI technology 1-gen-2017 Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander
Exploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology 1-gen-2020 Taco, R.; Yavits, L.; Shavit, N.; Stanger, I.; Lanuzza, M.; Fish, A.
Exploiting TFET-based technology for energy-efficient STT-MRAM cells 1-gen-2023 Perez, S. S.; Bedoya, A.; Procel, L. M.; Taco, Ramiro.