We present a mixed-signal ASIC, called ALCOR (A Low-power Chip for Optical sensor Readout), designed for the readout and digitization of signals from Silicon Photomultipliers (SiPMs) in the framework of the dual-radiator RICH (dRICH) detector of the electron–Proton/Ion Collider (ePIC) experiment at the Electron–Ion Collider (EIC). ALCOR features 32 channels arranged in an 8x4 matrix. The amplifier input stage is a low impedance current conveyor based on a regulated common-gate topology. The versatile front-end is able to work with positive or negative input polarity signals and includes four gain settings and two discriminators with 6-bit DAC programmable thresholds. Each channel also incorporates quad-buffered low-power TDCs based on analogue interpolation providing precise timestamping with a 25–50 ps time bin. ALCOR is designed in a 110 nm CMOS technology and the power consumption is about 10–12 mW per channel. The ASIC has been extensively tested in the laboratory standalone and coupled to different SiPM models to assess its functionality and performance. The results have been validated in a beam test campaign with a prototype of the dRICH detector and 1280 3 × 3 mm2 SiPM sensors.
ALCOR: A mixed-signal ASIC for the dRICH detector of the ePIC experiment at the EIC
Capua, M.;Fazio, S.;Occhiuto, L.;Tassi, E.;
2024-01-01
Abstract
We present a mixed-signal ASIC, called ALCOR (A Low-power Chip for Optical sensor Readout), designed for the readout and digitization of signals from Silicon Photomultipliers (SiPMs) in the framework of the dual-radiator RICH (dRICH) detector of the electron–Proton/Ion Collider (ePIC) experiment at the Electron–Ion Collider (EIC). ALCOR features 32 channels arranged in an 8x4 matrix. The amplifier input stage is a low impedance current conveyor based on a regulated common-gate topology. The versatile front-end is able to work with positive or negative input polarity signals and includes four gain settings and two discriminators with 6-bit DAC programmable thresholds. Each channel also incorporates quad-buffered low-power TDCs based on analogue interpolation providing precise timestamping with a 25–50 ps time bin. ALCOR is designed in a 110 nm CMOS technology and the power consumption is about 10–12 mW per channel. The ASIC has been extensively tested in the laboratory standalone and coupled to different SiPM models to assess its functionality and performance. The results have been validated in a beam test campaign with a prototype of the dRICH detector and 1280 3 × 3 mm2 SiPM sensors.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.