IRIS
PERRI, Stefania
 Distribuzione geografica
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Continente #
EU - Europa 68
Totale 68
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Nazione #
IT - Italia 68
Totale 68
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Città #
Rende 61
Castrolibero 3
Mascalucia 2
Catania 1
Gioia Tauro 1
Totale 68
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Nome #
Design of Efficient BCD adders in Quantum Dot Cellular Automata, file ddc632d3-6ab6-321f-e053-1705fe0abc09 6
Low-Power Level Shifter for Multi-Supply Voltage Designs, file ddc632d3-a51c-321f-e053-1705fe0abc09 6
VLSI circuits for low-power high-speed asynchronous addition, file ddc632d3-5627-321f-e053-1705fe0abc09 4
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology, file ddc632d3-5bad-321f-e053-1705fe0abc09 4
An efficient self-timed adder realized using conventional CMOS standard cells, file ddc632d3-5628-321f-e053-1705fe0abc09 3
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation, file ddc632d5-a8db-321f-e053-1705fe0abc09 3
Low bit rate image compression core for onboard space applications, file ddc632d3-4f68-321f-e053-1705fe0abc09 2
Design of efficient QCA multiplexers, file ddc632d3-5b33-321f-e053-1705fe0abc09 2
New methodology for the design of efficient binary addition circuits in QCA, file ddc632d3-665d-321f-e053-1705fe0abc09 2
Efficient reconfigurable Manchester adders for low-power media processing, file ddc632d3-706d-321f-e053-1705fe0abc09 2
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core, file ddc632d3-836b-321f-e053-1705fe0abc09 2
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications, file ddc632d3-8618-321f-e053-1705fe0abc09 2
An efficient wavelet image encoder for FPGA-based design, file ddc632d3-8637-321f-e053-1705fe0abc09 2
Designing High-Speed Adders in Power-Constrained Environments, file ddc632d3-a8fc-321f-e053-1705fe0abc09 2
Charge pump based subsystem for secure smart card design, file 3c753257-5807-428f-bade-76b3dcc711b0 1
FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis, file 3f4f1e18-2337-41e7-94e1-89cdca6ab37d 1
Techniques for leakage energy reduction in deep submicrometer cache memories, file ddc632d3-4ef3-321f-e053-1705fe0abc09 1
Low-power split-path data-driven dynamic logic, file ddc632d3-5639-321f-e053-1705fe0abc09 1
An Efficient Hardware-Oriented Stereo Matching Algorithm, file ddc632d3-6b38-321f-e053-1705fe0abc09 1
Power supply noise in accurate delay model for the sub-threshold domain, file ddc632d3-74f8-321f-e053-1705fe0abc09 1
Embedded surveillance system using background subtraction and Raspberry Pi, file ddc632d3-7b7f-321f-e053-1705fe0abc09 1
A novel background subtraction method based on color invariants and grayscale levels, file ddc632d3-7e5c-321f-e053-1705fe0abc09 1
56-bit self-timed adder for high speed asynchronous datapaths, file ddc632d3-812a-321f-e053-1705fe0abc09 1
A new low-power high-speed single-clock-cycle binary comparator, file ddc632d3-8157-321f-e053-1705fe0abc09 1
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors, file ddc632d3-898c-321f-e053-1705fe0abc09 1
Charge Pump Based System for Secure Smart-Card Design, file ddc632d3-93de-321f-e053-1705fe0abc09 1
SIMD 2-D Convolver for Fast FPGA-based Image and Video Processors, file ddc632d3-9b02-321f-e053-1705fe0abc09 1
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems, file ddc632d3-9c09-321f-e053-1705fe0abc09 1
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs, file ddc632d3-9d2d-321f-e053-1705fe0abc09 1
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics, file ddc632d3-9dd6-321f-e053-1705fe0abc09 1
Variable precision arithmetic circuits for FPGA-based multimedia processors, file ddc632d3-a22d-321f-e053-1705fe0abc09 1
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain, file ddc632d3-a3f9-321f-e053-1705fe0abc09 1
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications, file ddc632d3-a739-321f-e053-1705fe0abc09 1
A high-performance fully reconfigurable FPGA-based 2D convolution processor, file ddc632d3-a8ba-321f-e053-1705fe0abc09 1
Comparative analysis of yield optimized pulsed flip-flops, file ddc632d3-b04a-321f-e053-1705fe0abc09 1
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations, file ddc632d3-b0ab-321f-e053-1705fe0abc09 1
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates, file ddc632d3-b17d-321f-e053-1705fe0abc09 1
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing, file ddc632d3-bb14-321f-e053-1705fe0abc09 1
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs, file ddc632d4-4bbb-321f-e053-1705fe0abc09 1
Impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis, file ddc632d4-5155-321f-e053-1705fe0abc09 1
Totale 68
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Categoria #
all - tutte 69
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 69
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/202116 0 0 0 0 0 0 1 5 9 0 1 0
2021/20223 0 0 0 0 0 0 0 0 0 0 0 3
2022/20232 2 0 0 0 0 0 0 0 0 0 0 0
2023/20243 0 0 2 0 0 0 0 0 0 1 0 0
Totale 68