IRIS
PERRI, Stefania
 Distribuzione geografica
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Continente #
NA - Nord America 6.473
AS - Asia 6.071
EU - Europa 3.306
SA - Sud America 1.845
AF - Africa 445
OC - Oceania 15
Continente sconosciuto - Info sul continente non disponibili 11
Totale 18.166
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Nazione #
US - Stati Uniti d'America 6.191
SG - Singapore 2.412
BR - Brasile 1.341
UA - Ucraina 1.121
CN - Cina 1.108
VN - Vietnam 1.000
DE - Germania 728
IT - Italia 385
HK - Hong Kong 373
SE - Svezia 255
FR - Francia 246
TR - Turchia 197
SN - Senegal 186
AR - Argentina 173
IN - India 162
KR - Corea 160
CA - Canada 151
FI - Finlandia 134
BD - Bangladesh 125
IQ - Iraq 107
GB - Regno Unito 85
ID - Indonesia 77
EC - Ecuador 72
CO - Colombia 71
MX - Messico 69
RU - Federazione Russa 67
ZA - Sudafrica 67
PK - Pakistan 59
VE - Venezuela 59
AT - Austria 49
MA - Marocco 42
CL - Cile 41
BE - Belgio 40
PL - Polonia 38
PY - Paraguay 37
EG - Egitto 34
SA - Arabia Saudita 32
NL - Olanda 31
TN - Tunisia 31
UZ - Uzbekistan 31
ES - Italia 30
JO - Giordania 24
PE - Perù 23
PH - Filippine 23
NP - Nepal 20
DZ - Algeria 18
KE - Kenya 18
KZ - Kazakistan 17
MY - Malesia 17
ET - Etiopia 16
JP - Giappone 16
UY - Uruguay 16
DO - Repubblica Dominicana 15
IL - Israele 15
AE - Emirati Arabi Uniti 13
AU - Australia 12
CR - Costa Rica 12
KG - Kirghizistan 12
AZ - Azerbaigian 10
OM - Oman 10
PA - Panama 10
BO - Bolivia 9
RS - Serbia 9
CZ - Repubblica Ceca 8
LB - Libano 8
RO - Romania 8
AL - Albania 7
BY - Bielorussia 7
EU - Europa 7
AM - Armenia 6
BG - Bulgaria 6
CH - Svizzera 6
MK - Macedonia 6
NI - Nicaragua 6
CI - Costa d'Avorio 5
IE - Irlanda 5
LT - Lituania 5
LY - Libia 5
TW - Taiwan 5
BA - Bosnia-Erzegovina 4
GE - Georgia 4
GR - Grecia 4
HR - Croazia 4
IR - Iran 4
JM - Giamaica 4
KW - Kuwait 4
LK - Sri Lanka 4
LV - Lettonia 4
PS - Palestinian Territory 4
XK - ???statistics.table.value.countryCode.XK??? 4
AO - Angola 3
BW - Botswana 3
DK - Danimarca 3
GA - Gabon 3
GT - Guatemala 3
HN - Honduras 3
TH - Thailandia 3
BB - Barbados 2
BF - Burkina Faso 2
KH - Cambogia 2
Totale 18.123
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Città #
Singapore 1.013
Chandler 854
Jacksonville 732
San Jose 477
Dallas 400
Boardman 398
Ho Chi Minh City 378
Dearborn 374
Hong Kong 365
Beijing 299
Ashburn 283
San Mateo 237
Hanoi 224
Dakar 186
Lawrence 169
Roxbury 169
Lauterbourg 162
Seoul 157
Izmir 144
Hefei 141
Shanghai 141
Des Moines 117
Ann Arbor 109
Ottawa 109
Rende 104
Helsinki 103
São Paulo 95
Cambridge 85
Bremen 75
New York 67
Council Bluffs 62
Inglewood 60
The Dalles 59
Ogden 58
Munich 51
Brooklyn 47
Columbus 47
Los Angeles 46
Haiphong 45
Milan 41
Rio de Janeiro 41
Grafing 37
Brussels 36
Santa Clara 35
Baghdad 34
Da Nang 34
Guangzhou 34
Wilmington 33
Vienna 32
Tianjin 31
Catanzaro 30
Quito 29
Dhaka 28
Tashkent 27
Turku 27
Warsaw 27
Seattle 26
Campinas 25
Johannesburg 25
San Francisco 25
Frankfurt am Main 22
Amman 21
Belo Horizonte 21
Mexico City 21
Orem 21
Asunción 20
Biên Hòa 20
Chennai 20
Curitiba 20
Guayaquil 20
Caracas 19
Hải Dương 18
Istanbul 18
Thái Bình 18
Bogotá 17
Lahore 17
Toronto 17
Brasília 16
Guarulhos 16
Lima 16
Nuremberg 16
Porto Alegre 16
Shenzhen 16
Addis Ababa 15
Amsterdam 15
New Delhi 15
Bari 14
Falkenstein 14
London 14
Medellín 14
Naples 14
Salvador 14
Santiago 14
Buenos Aires 13
Can Tho 13
Cape Town 13
Erbil 13
Nairobi 13
Sorocaba 13
Tunis 13
Totale 9.959
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Nome #
A high-performance fully reconfigurable FPGA-based 2D convolution processor 184
A Matrix Product Accelerator for Field Programmable Systems on Chip 163
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 162
A 56-bit self-timed adder for high speed asynchronous datapath 161
A FPSoC for wavelet-based image compression 160
A high-speed energy-efficient 64-bit reconfigurable binary adder 158
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations 151
56-bit self-timed adder for high speed asynchronous datapaths 150
A new reconfigurable coarse-grain architecture for multimedia applications 149
A high flexible early-late gate bit synchronizer in FPGA-based software defined radios 145
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 145
An efficient hardware-oriented single-pass approach for connected component analysis 143
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 140
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 140
A high flexible 8-bit and 16-bit SIMD soft microcontroller for FPGAs 139
64-bit reconfigurable adder for low power media processing 139
A Low-Power Sub-Nanosecond Standard-Cells Based Adder 137
A new low-power high-speed single-clock-cycle binary comparator 137
A microchip integrated wireless sensor for the monitoring of high concentration photo-voltaic solar cells 136
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 135
A matrix product coprocessor for FPGA embedded soft processors 134
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 133
A Microchip Integrated Sensor for the Monitoring of High Concentration Photo-voltaic Solar Modules 133
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 132
High speed division and square root modules for asynchronous datapaths 131
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 130
A new charge-pump based countermeasure against differential power analysis 129
An efficient connected component labeling architecture for embedded systems 129
A New High Performance Circuit for Statistical Carry Lookahead Addition 128
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 128
Multimodal background subtraction for high-performance embedded systems 127
A novel background subtraction method based on color invariants and grayscale levels 127
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 122
An efficient wavelet image encoder for FPGA-based design 121
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 121
Techniques for leakage energy reduction in deep submicrometer cache memories 120
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems 120
An explainable embedded neural system for on-board ship detection from optical satellite imagery 119
Learning Style Identification by CHAEA Junior Questionnaire and Artificial Neural Network Method: A Case Study 119
A parallel connected component labeling architecture for heterogeneous systems-on-chip 119
High speed self-timed pipelined datapath for square rooting 118
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 118
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 116
Comparative analysis of yield optimized pulsed flip-flops 115
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 115
Design of Real-Time FPGA-based Embedded System for Stereo Vision 115
Variable precision arithmetic circuits for FPGA-based multimedia processors 114
Low-Power Level Shifter for Multi-Supply Voltage Designs 113
An efficient convolution engine based on the à-trous spatial pyramid pooling 113
Accurate power estimation model for CMOS adders optimization 112
A Fast Carry Chain Adder for Virtex-5 FPGAs 111
Low-power split-path data-driven dynamic logic 110
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology 109
A new type of fast, low-cost binary adder 108
Hybrid carry-select statistical carry look-ahead adder 107
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing 107
An efficient self-timed adder realized using conventional CMOS standard cells 106
New methodology for the design of efficient binary addition circuits in QCA 106
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 105
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals 105
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 104
Adaptive Census transform: A novel hardware-oriented stereovision algorithm 104
Educational Design of high performance arithmetic circuits 104
An Efficient Hardware-Oriented Stereo Matching Algorithm 104
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 104
Low bit rate image compression core for onboard space applications 104
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation 104
New high performance circuit for statistical carry lookahead addition 103
Fast, low-cost adders using carry-strength signals 103
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits 102
Educational design of high-performance arithmetic circuits on FPGA 102
Efficient VLSI implementation of statistical carry lookahead adder 102
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 102
VLSI circuits for low-power high-speed asynchronous addition 101
Design of efficient QCA multiplexers 101
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 101
A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations 100
Area-time-power tradeoff in VLSI cellular arrays implementations 100
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines 100
Energy‐efficient architecture for CNNs inference on heterogeneous FPGA 100
High speed division and square root modules for asynchronous datapath 99
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 99
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 98
Area-delay efficient binary adders in QCA 98
High speed self-timed pipelined datapath for square root 98
Embedded surveillance system using background subtraction and Raspberry Pi 98
Multimodal background subtraction for high-performance embedded systems 98
Design of a real-time face detection architecture for heterogeneous systems-on-chips 96
An embedded machine vision system for an in-line quality check of assembly processes 96
Design of Efficient BCD adders in Quantum Dot Cellular Automata 95
Circuito integrato digitale per operazioni di somma binaria in sistemi asincroni ad alta velocità 95
Design of Approximate Bilateral Filters for Image Denoising on FPGAs 94
Design of a Low-Power Super-Resolution Architecture for Virtual Reality Wearable Devices 94
High performance square rooting circuit using hybrid radix-2 adders 94
Design of 3 : 1 multiplexer standard cell 94
Designing High-Speed Adders in Power-Constrained Environments 94
Fast and energy-efficient Manchester Carry by-pass adders 94
Efficient approximate adders for fpga-based data-paths 94
Designing Fast Convolutional Engines for Deep Learning Applications 94
Stereo vision architecture for heterogeneous systems-on-chip 93
Totale 11.679
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Categoria #
all - tutte 106.239
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 106.239
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021316 0 0 0 0 0 0 0 0 0 168 9 139
2021/20221.530 12 201 1 92 155 47 10 278 17 15 248 454
2022/20231.884 200 138 24 221 260 223 7 330 244 72 84 81
2023/2024965 130 48 83 44 44 64 21 81 104 30 82 234
2024/20252.856 91 472 74 119 235 120 96 215 418 113 277 626
2025/20267.987 1.041 433 742 1.013 1.532 548 901 432 642 703 0 0
Totale 18.348