IRIS
PERRI, Stefania
 Distribuzione geografica
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Continente #
NA - Nord America 5.686
AS - Asia 4.712
EU - Europa 2.909
SA - Sud America 1.412
AF - Africa 312
OC - Oceania 11
Continente sconosciuto - Info sul continente non disponibili 9
Totale 15.051
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Nazione #
US - Stati Uniti d'America 5.465
SG - Singapore 2.144
UA - Ucraina 1.110
BR - Brasile 1.076
CN - Cina 941
DE - Germania 703
VN - Vietnam 572
HK - Hong Kong 323
IT - Italia 323
SE - Svezia 253
SN - Senegal 182
TR - Turchia 166
KR - Corea 158
CA - Canada 142
AR - Argentina 130
FI - Finlandia 128
IN - India 75
FR - Francia 66
GB - Regno Unito 59
BD - Bangladesh 58
IQ - Iraq 58
RU - Federazione Russa 51
EC - Ecuador 50
ID - Indonesia 50
AT - Austria 43
MX - Messico 41
ZA - Sudafrica 41
CO - Colombia 37
BE - Belgio 36
CL - Cile 28
PY - Paraguay 28
VE - Venezuela 28
PK - Pakistan 27
NL - Olanda 25
PL - Polonia 25
EG - Egitto 21
MA - Marocco 21
ES - Italia 18
JO - Giordania 18
PE - Perù 14
UY - Uruguay 13
UZ - Uzbekistan 12
IL - Israele 11
JP - Giappone 11
DO - Repubblica Dominicana 10
ET - Etiopia 10
KE - Kenya 10
KG - Kirghizistan 10
NP - Nepal 10
TN - Tunisia 10
KZ - Kazakistan 9
SA - Arabia Saudita 9
AU - Australia 8
AZ - Azerbaigian 7
CZ - Repubblica Ceca 7
EU - Europa 7
RS - Serbia 7
AL - Albania 6
CR - Costa Rica 6
DZ - Algeria 6
LB - Libano 6
AE - Emirati Arabi Uniti 5
AM - Armenia 5
BO - Bolivia 5
CH - Svizzera 5
LT - Lituania 5
PA - Panama 5
RO - Romania 5
BG - Bulgaria 4
BY - Bielorussia 4
IR - Iran 4
MK - Macedonia 4
OM - Oman 4
TW - Taiwan 4
BW - Botswana 3
CI - Costa d'Avorio 3
GR - Grecia 3
GT - Guatemala 3
HR - Croazia 3
KW - Kuwait 3
LV - Lettonia 3
MY - Malesia 3
NI - Nicaragua 3
AO - Angola 2
BA - Bosnia-Erzegovina 2
BB - Barbados 2
GE - Georgia 2
HN - Honduras 2
IE - Irlanda 2
JM - Giamaica 2
KI - Kiribati 2
LU - Lussemburgo 2
PT - Portogallo 2
SV - El Salvador 2
SY - Repubblica araba siriana 2
XK - ???statistics.table.value.countryCode.XK??? 2
BF - Burkina Faso 1
BH - Bahrain 1
BS - Bahamas 1
CU - Cuba 1
Totale 15.035
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Città #
Chandler 854
Singapore 820
Jacksonville 732
Boardman 398
Dallas 397
Dearborn 374
Hong Kong 315
Beijing 259
San Mateo 237
Ho Chi Minh City 219
Dakar 182
Lawrence 169
Roxbury 169
Ashburn 158
Seoul 157
Izmir 142
Hefei 141
Shanghai 138
Hanoi 121
Des Moines 117
Ann Arbor 109
Ottawa 107
Rende 104
Helsinki 97
Cambridge 85
São Paulo 81
Bremen 74
Inglewood 60
Ogden 58
The Dalles 57
Council Bluffs 51
Munich 51
New York 51
Columbus 47
Brooklyn 46
Los Angeles 42
Grafing 37
Brussels 36
Rio de Janeiro 34
Wilmington 33
Catanzaro 30
Haiphong 30
Turku 27
Vienna 27
Santa Clara 26
Seattle 26
San Francisco 25
Tianjin 25
Milan 23
Quito 21
Guangzhou 20
Baghdad 19
Warsaw 19
Biên Hòa 18
Da Nang 18
Belo Horizonte 17
Amman 16
Asunción 16
Johannesburg 16
Toronto 16
Curitiba 15
Dhaka 15
Frankfurt am Main 15
Bari 14
Campinas 14
Falkenstein 14
Chennai 13
Guarulhos 13
Guayaquil 13
Mexico City 13
Naples 13
Porto Alegre 13
Juiz de Fora 12
Nanjing 12
Amsterdam 11
Brasília 11
Chicago 11
Hải Dương 11
Lima 11
London 11
Nuremberg 11
Thái Bình 11
Can Tho 10
Fortaleza 10
Joinville 10
Montevideo 10
Norwalk 10
Tokyo 10
Addis Ababa 9
Betim 9
Bishkek 9
Bogotá 9
Buenos Aires 9
Maracaibo 9
Nairobi 9
Quảng Ngãi 9
Shenzhen 9
Sorocaba 9
Tashkent 9
Boston 8
Totale 8.238
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Nome #
A high-performance fully reconfigurable FPGA-based 2D convolution processor 159
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 138
A 56-bit self-timed adder for high speed asynchronous datapath 135
A FPSoC for wavelet-based image compression 135
A high-speed energy-efficient 64-bit reconfigurable binary adder 130
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations 129
A high flexible early-late gate bit synchronizer in FPGA-based software defined radios 126
56-bit self-timed adder for high speed asynchronous datapaths 126
A Matrix Product Accelerator for Field Programmable Systems on Chip 125
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 125
An efficient hardware-oriented single-pass approach for connected component analysis 124
A high flexible 8-bit and 16-bit SIMD soft microcontroller for FPGAs 124
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 121
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 118
A Low-Power Sub-Nanosecond Standard-Cells Based Adder 116
A new charge-pump based countermeasure against differential power analysis 116
A new reconfigurable coarse-grain architecture for multimedia applications 116
High speed division and square root modules for asynchronous datapaths 115
A matrix product coprocessor for FPGA embedded soft processors 115
A new low-power high-speed single-clock-cycle binary comparator 114
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 113
A microchip integrated wireless sensor for the monitoring of high concentration photo-voltaic solar cells 113
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 113
A New High Performance Circuit for Statistical Carry Lookahead Addition 112
A Microchip Integrated Sensor for the Monitoring of High Concentration Photo-voltaic Solar Modules 111
64-bit reconfigurable adder for low power media processing 111
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 110
A novel background subtraction method based on color invariants and grayscale levels 109
Multimodal background subtraction for high-performance embedded systems 107
High speed self-timed pipelined datapath for square rooting 106
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 106
An efficient connected component labeling architecture for embedded systems 104
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 103
Techniques for leakage energy reduction in deep submicrometer cache memories 102
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 102
An efficient wavelet image encoder for FPGA-based design 101
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 101
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 101
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 100
Learning Style Identification by CHAEA Junior Questionnaire and Artificial Neural Network Method: A Case Study 99
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 97
A Fast Carry Chain Adder for Virtex-5 FPGAs 96
A new type of fast, low-cost binary adder 96
An explainable embedded neural system for on-board ship detection from optical satellite imagery 95
Low-Power Level Shifter for Multi-Supply Voltage Designs 95
Comparative analysis of yield optimized pulsed flip-flops 95
Variable precision arithmetic circuits for FPGA-based multimedia processors 94
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing 94
Accurate power estimation model for CMOS adders optimization 94
A parallel connected component labeling architecture for heterogeneous systems-on-chip 94
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems 94
An Efficient Hardware-Oriented Stereo Matching Algorithm 92
Fast, low-cost adders using carry-strength signals 92
Design of Real-Time FPGA-based Embedded System for Stereo Vision 92
An efficient convolution engine based on the à-trous spatial pyramid pooling 92
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits 91
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 91
Hybrid carry-select statistical carry look-ahead adder 90
Low-power split-path data-driven dynamic logic 90
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines 90
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 90
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology 90
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation 88
Adaptive Census transform: A novel hardware-oriented stereovision algorithm 86
High speed self-timed pipelined datapath for square root 86
Low bit rate image compression core for onboard space applications 86
VLSI circuits for low-power high-speed asynchronous addition 85
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 85
Area-delay efficient binary adders in QCA 85
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 85
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 85
Educational Design of high performance arithmetic circuits 84
Design of Efficient BCD adders in Quantum Dot Cellular Automata 84
Educational design of high-performance arithmetic circuits on FPGA 84
New methodology for the design of efficient binary addition circuits in QCA 84
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 84
Efficient VLSI implementation of statistical carry lookahead adder 84
Multimodal background subtraction for high-performance embedded systems 84
Area-time-power tradeoff in VLSI cellular arrays implementations 83
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 83
Embedded surveillance system using background subtraction and Raspberry Pi 83
Energy‐efficient architecture for CNNs inference on heterogeneous FPGA 83
High speed division and square root modules for asynchronous datapath 82
New high performance circuit for statistical carry lookahead addition 82
Design of efficient QCA multiplexers 82
Stereo vision architecture for heterogeneous systems-on-chip 82
Circuito integrato digitale per operazioni di somma binaria in sistemi asincroni ad alta velocità 81
Designing Fast Convolutional Engines for Deep Learning Applications 81
An embedded machine vision system for an in-line quality check of assembly processes 81
Design of Approximate Bilateral Filters for Image Denoising on FPGAs 80
Designing High-Speed Adders in Power-Constrained Environments 80
High performance square rooting circuit using hybrid radix-2 adders 79
Color Invariant Study for Background Subtraction 79
Sad-Based Stereo Matching Circuit for FPGAs 79
Design of a Low-Power Super-Resolution Architecture for Virtual Reality Wearable Devices 78
Approximate Multipliers with Dynamic Truncation for Energy Reduction via Graceful Quality Degradation 78
Fast and energy-efficient Manchester Carry by-pass adders 77
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals 77
An efficient self-timed adder realized using conventional CMOS standard cells 76
Efficient Recursive Multiply Architecture for FPGAs 75
Totale 9.795
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Categoria #
all - tutte 100.290
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 100.290
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021673 0 0 0 0 0 150 11 177 19 168 9 139
2021/20221.530 12 201 1 92 155 47 10 278 17 15 248 454
2022/20231.884 200 138 24 221 260 223 7 330 244 72 84 81
2023/2024965 130 48 83 44 44 64 21 81 104 30 82 234
2024/20252.856 91 472 74 119 235 120 96 215 418 113 277 626
2025/20264.871 1.041 433 742 1.013 1.532 110 0 0 0 0 0 0
Totale 15.232