IRIS
PERRI, Stefania
 Distribuzione geografica
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Continente #
NA - Nord America 7.617
AS - Asia 6.426
EU - Europa 3.538
SA - Sud America 1.873
AF - Africa 451
Continente sconosciuto - Info sul continente non disponibili 196
OC - Oceania 16
Totale 20.117
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Nazione #
US - Stati Uniti d'America 7.276
SG - Singapore 2.456
BR - Brasile 1.359
CN - Cina 1.215
UA - Ucraina 1.123
VN - Vietnam 1.008
DE - Germania 731
IT - Italia 582
HK - Hong Kong 381
BD - Bangladesh 275
SE - Svezia 255
FR - Francia 248
TR - Turchia 198
SN - Senegal 186
AR - Argentina 175
CA - Canada 174
IN - India 171
KR - Corea 161
FI - Finlandia 134
IQ - Iraq 107
GB - Regno Unito 101
ID - Indonesia 82
CO - Colombia 75
EC - Ecuador 75
MX - Messico 74
RU - Federazione Russa 67
ZA - Sudafrica 67
PK - Pakistan 62
VE - Venezuela 60
AT - Austria 49
BE - Belgio 42
MA - Marocco 42
CL - Cile 41
PL - Polonia 38
PY - Paraguay 37
EG - Egitto 34
ES - Italia 34
TN - Tunisia 33
SA - Arabia Saudita 32
NL - Olanda 31
UZ - Uzbekistan 31
PH - Filippine 25
JO - Giordania 24
NP - Nepal 24
PE - Perù 23
MY - Malesia 22
JP - Giappone 20
DZ - Algeria 19
KE - Kenya 19
KZ - Kazakistan 17
AE - Emirati Arabi Uniti 16
CR - Costa Rica 16
ET - Etiopia 16
UY - Uruguay 16
DO - Repubblica Dominicana 15
IL - Israele 15
JM - Giamaica 14
AU - Australia 12
KG - Kirghizistan 12
AZ - Azerbaigian 10
OM - Oman 10
PA - Panama 10
BO - Bolivia 9
RO - Romania 9
RS - Serbia 9
CZ - Repubblica Ceca 8
LB - Libano 8
NI - Nicaragua 8
AL - Albania 7
BY - Bielorussia 7
EU - Europa 7
AM - Armenia 6
BG - Bulgaria 6
CH - Svizzera 6
CI - Costa d'Avorio 6
GT - Guatemala 6
IE - Irlanda 6
MK - Macedonia 6
SV - El Salvador 6
GR - Grecia 5
HN - Honduras 5
HR - Croazia 5
LT - Lituania 5
LY - Libia 5
TW - Taiwan 5
XK - ???statistics.table.value.countryCode.XK??? 5
BA - Bosnia-Erzegovina 4
GE - Georgia 4
IR - Iran 4
KW - Kuwait 4
LK - Sri Lanka 4
LV - Lettonia 4
PR - Porto Rico 4
PS - Palestinian Territory 4
AO - Angola 3
BB - Barbados 3
BW - Botswana 3
DK - Danimarca 3
GA - Gabon 3
MD - Moldavia 3
Totale 19.882
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Città #
Singapore 1.028
Chandler 854
Jacksonville 735
Council Bluffs 542
San Jose 500
Dallas 411
Boardman 398
Ashburn 381
Ho Chi Minh City 380
Dearborn 374
Hong Kong 371
Beijing 325
San Mateo 237
Hanoi 228
Dakar 186
Lawrence 169
Roxbury 169
Lauterbourg 162
Seoul 157
Izmir 144
Hefei 142
Shanghai 142
New York 130
Santa Clara 124
Des Moines 117
Ottawa 110
Ann Arbor 109
Rende 105
Helsinki 103
São Paulo 102
Milan 96
Cambridge 85
Bremen 75
Columbus 72
Inglewood 60
Los Angeles 59
The Dalles 59
Ogden 58
Munich 51
Brooklyn 48
Rome 46
Haiphong 45
Rio de Janeiro 41
Grafing 37
Brussels 36
Guangzhou 35
Baghdad 34
Da Nang 34
Wilmington 34
Tianjin 33
Dhaka 32
Vienna 32
Catanzaro 30
London 30
Quito 30
Toronto 28
San Francisco 27
Seattle 27
Tashkent 27
Turku 27
Warsaw 27
Campinas 25
Johannesburg 25
Frankfurt am Main 24
Buffalo 23
Mexico City 23
Amman 21
Belo Horizonte 21
Guayaquil 21
Naples 21
Omaha 21
Orem 21
Asunción 20
Biên Hòa 20
Chennai 20
Chicago 20
Curitiba 20
Bogotá 19
Caracas 19
Hải Dương 18
Istanbul 18
Mumbai 18
Thái Bình 18
Bari 17
Lahore 17
Porto Alegre 17
Shenzhen 17
Brasília 16
Guarulhos 16
Lima 16
Nuremberg 16
Phoenix 16
Addis Ababa 15
Amsterdam 15
New Delhi 15
Falkenstein 14
Medellín 14
Nairobi 14
Salvador 14
Santiago 14
Totale 11.009
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Nome #
A high-performance fully reconfigurable FPGA-based 2D convolution processor 214
A Matrix Product Accelerator for Field Programmable Systems on Chip 190
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 172
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 171
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems 169
A high-speed energy-efficient 64-bit reconfigurable binary adder 168
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations 167
A new reconfigurable coarse-grain architecture for multimedia applications 166
A FPSoC for wavelet-based image compression 166
A 56-bit self-timed adder for high speed asynchronous datapath 165
An efficient hardware-oriented single-pass approach for connected component analysis 159
56-bit self-timed adder for high speed asynchronous datapaths 158
Multimodal background subtraction for high-performance embedded systems 157
A high flexible early-late gate bit synchronizer in FPGA-based software defined radios 150
64-bit reconfigurable adder for low power media processing 145
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 145
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 144
A Low-Power Sub-Nanosecond Standard-Cells Based Adder 143
A high flexible 8-bit and 16-bit SIMD soft microcontroller for FPGAs 143
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 143
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 143
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 142
An efficient connected component labeling architecture for embedded systems 142
A new low-power high-speed single-clock-cycle binary comparator 141
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 141
A Microchip Integrated Sensor for the Monitoring of High Concentration Photo-voltaic Solar Modules 140
A microchip integrated wireless sensor for the monitoring of high concentration photo-voltaic solar cells 139
A matrix product coprocessor for FPGA embedded soft processors 138
An efficient wavelet image encoder for FPGA-based design 137
Low-power split-path data-driven dynamic logic 136
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 136
High speed division and square root modules for asynchronous datapaths 133
Techniques for leakage energy reduction in deep submicrometer cache memories 133
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 133
A parallel connected component labeling architecture for heterogeneous systems-on-chip 132
A novel background subtraction method based on color invariants and grayscale levels 131
A New High Performance Circuit for Statistical Carry Lookahead Addition 131
A new charge-pump based countermeasure against differential power analysis 130
Design of Real-Time FPGA-based Embedded System for Stereo Vision 129
A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations 128
An efficient self-timed adder realized using conventional CMOS standard cells 128
Design of a real-time face detection architecture for heterogeneous systems-on-chips 127
An explainable embedded neural system for on-board ship detection from optical satellite imagery 126
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 126
Variable precision arithmetic circuits for FPGA-based multimedia processors 125
Comparative analysis of yield optimized pulsed flip-flops 125
Learning Style Identification by CHAEA Junior Questionnaire and Artificial Neural Network Method: A Case Study 125
High speed self-timed pipelined datapath for square rooting 124
Low-Power Level Shifter for Multi-Supply Voltage Designs 124
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals 124
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 124
Hybrid carry-select statistical carry look-ahead adder 122
An efficient convolution engine based on the à-trous spatial pyramid pooling 122
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 121
Educational Design of high performance arithmetic circuits 120
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits 120
A Fast Carry Chain Adder for Virtex-5 FPGAs 120
New methodology for the design of efficient binary addition circuits in QCA 119
Low bit rate image compression core for onboard space applications 119
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 118
Efficient deconvolution architecture for heterogeneous systems-on-chip 118
Accurate power estimation model for CMOS adders optimization 116
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 115
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology 115
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation 114
Design of efficient QCA multiplexers 113
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 113
Multimodal background subtraction for high-performance embedded systems 113
Adaptive Census transform: A novel hardware-oriented stereovision algorithm 112
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing 112
Efficient VLSI implementation of statistical carry lookahead adder 112
A new type of fast, low-cost binary adder 111
Educational design of high-performance arithmetic circuits on FPGA 111
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 111
Fast, low-cost adders using carry-strength signals 110
VLSI circuits for low-power high-speed asynchronous addition 109
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 109
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 108
Energy‐efficient architecture for CNNs inference on heterogeneous FPGA 108
New high performance circuit for statistical carry lookahead addition 107
An Efficient Hardware-Oriented Stereo Matching Algorithm 107
High speed self-timed pipelined datapath for square root 106
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines 106
Embedded surveillance system using background subtraction and Raspberry Pi 106
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 106
Design of a Low-Power Super-Resolution Architecture for Virtual Reality Wearable Devices 105
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 105
Fast and energy-efficient Manchester Carry by-pass adders 105
Efficient approximate adders for fpga-based data-paths 105
Design of Approximate Bilateral Filters for Image Denoising on FPGAs 104
Design of Efficient BCD adders in Quantum Dot Cellular Automata 104
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor 104
Designing High-Speed Adders in Power-Constrained Environments 104
An embedded machine vision system for an in-line quality check of assembly processes 104
High speed division and square root modules for asynchronous datapath 103
Design of 3 : 1 multiplexer standard cell 103
Area-delay efficient binary adders in QCA 103
Design and Implementation of a 90nm low bit-rate image compression core 103
Circuito integrato digitale per operazioni di somma binaria in sistemi asincroni ad alta velocità 103
High performance square rooting circuit using hybrid radix-2 adders 102
Totale 12.734
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Categoria #
all - tutte 115.296
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 115.296
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20221.518 0 201 1 92 155 47 10 278 17 15 248 454
2022/20231.884 200 138 24 221 260 223 7 330 244 72 84 81
2023/2024965 130 48 83 44 44 64 21 81 104 30 82 234
2024/20252.856 91 472 74 119 235 120 96 215 418 113 277 626
2025/20268.971 1.041 433 742 1.013 1.532 548 901 432 642 735 416 536
2026/2027785 586 199 0 0 0 0 0 0 0 0 0 0
Totale 20.117