IRIS
PERRI, Stefania
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
NA - Nord America 7.035
AS - Asia 6.310
EU - Europa 3.407
SA - Sud America 1.846
AF - Africa 448
OC - Oceania 16
Continente sconosciuto - Info sul continente non disponibili 11
Totale 19.073
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 6.721
SG - Singapore 2.448
BR - Brasile 1.341
CN - Cina 1.177
UA - Ucraina 1.121
VN - Vietnam 1.001
DE - Germania 728
IT - Italia 480
HK - Hong Kong 379
SE - Svezia 255
FR - Francia 246
BD - Bangladesh 236
TR - Turchia 197
SN - Senegal 186
AR - Argentina 173
CA - Canada 163
IN - India 162
KR - Corea 161
FI - Finlandia 134
IQ - Iraq 107
GB - Regno Unito 86
ID - Indonesia 79
EC - Ecuador 72
CO - Colombia 71
MX - Messico 70
RU - Federazione Russa 67
ZA - Sudafrica 67
PK - Pakistan 60
VE - Venezuela 60
AT - Austria 49
BE - Belgio 42
MA - Marocco 42
CL - Cile 41
PL - Polonia 38
PY - Paraguay 37
EG - Egitto 34
ES - Italia 32
SA - Arabia Saudita 32
TN - Tunisia 32
NL - Olanda 31
UZ - Uzbekistan 31
JO - Giordania 24
NP - Nepal 24
PE - Perù 23
PH - Filippine 23
MY - Malesia 21
DZ - Algeria 19
KE - Kenya 18
JP - Giappone 17
KZ - Kazakistan 17
ET - Etiopia 16
UY - Uruguay 16
AE - Emirati Arabi Uniti 15
DO - Repubblica Dominicana 15
IL - Israele 15
CR - Costa Rica 14
AU - Australia 12
KG - Kirghizistan 12
AZ - Azerbaigian 10
OM - Oman 10
PA - Panama 10
BO - Bolivia 9
RS - Serbia 9
CZ - Repubblica Ceca 8
JM - Giamaica 8
LB - Libano 8
NI - Nicaragua 8
RO - Romania 8
AL - Albania 7
BY - Bielorussia 7
EU - Europa 7
AM - Armenia 6
BG - Bulgaria 6
CH - Svizzera 6
GT - Guatemala 6
MK - Macedonia 6
CI - Costa d'Avorio 5
IE - Irlanda 5
LT - Lituania 5
LY - Libia 5
TW - Taiwan 5
BA - Bosnia-Erzegovina 4
GE - Georgia 4
GR - Grecia 4
HN - Honduras 4
HR - Croazia 4
IR - Iran 4
KW - Kuwait 4
LK - Sri Lanka 4
LV - Lettonia 4
PS - Palestinian Territory 4
SV - El Salvador 4
XK - ???statistics.table.value.countryCode.XK??? 4
AO - Angola 3
BB - Barbados 3
BW - Botswana 3
DK - Danimarca 3
GA - Gabon 3
MD - Moldavia 3
PR - Porto Rico 3
Totale 19.023
Salva come PNG Salva come JPEG
Città #
Singapore 1.020
Chandler 854
Jacksonville 734
San Jose 500
Dallas 403
Boardman 398
Ho Chi Minh City 378
Dearborn 374
Hong Kong 369
Ashburn 329
Beijing 310
Council Bluffs 290
San Mateo 237
Hanoi 225
Dakar 186
Lawrence 169
Roxbury 169
Lauterbourg 162
Seoul 157
Izmir 144
Hefei 142
Shanghai 141
Des Moines 117
New York 111
Ottawa 110
Ann Arbor 109
Rende 105
Helsinki 103
São Paulo 95
Cambridge 85
Bremen 75
Columbus 72
Inglewood 60
The Dalles 59
Ogden 58
Santa Clara 58
Los Angeles 52
Munich 51
Brooklyn 48
Milan 46
Haiphong 45
Rio de Janeiro 41
Grafing 37
Brussels 36
Guangzhou 35
Baghdad 34
Da Nang 34
Tianjin 33
Wilmington 33
Vienna 32
Catanzaro 30
Dhaka 29
Quito 29
Seattle 27
Tashkent 27
Turku 27
Warsaw 27
San Francisco 26
Campinas 25
Johannesburg 25
Rome 23
Frankfurt am Main 22
Mexico City 22
Amman 21
Belo Horizonte 21
Orem 21
Toronto 21
Asunción 20
Biên Hòa 20
Buffalo 20
Chennai 20
Curitiba 20
Guayaquil 20
Naples 20
Caracas 19
Chicago 19
Hải Dương 18
Istanbul 18
Thái Bình 18
Bogotá 17
Lahore 17
Shenzhen 17
Bari 16
Brasília 16
Guarulhos 16
Lima 16
Nuremberg 16
Porto Alegre 16
Addis Ababa 15
Amsterdam 15
New Delhi 15
Falkenstein 14
London 14
Medellín 14
Salvador 14
Santiago 14
Tunis 14
Buenos Aires 13
Can Tho 13
Cape Town 13
Totale 10.435
Salva come PNG Salva come JPEG
Nome #
A high-performance fully reconfigurable FPGA-based 2D convolution processor 200
A Matrix Product Accelerator for Field Programmable Systems on Chip 183
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 168
A FPSoC for wavelet-based image compression 165
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations 163
A 56-bit self-timed adder for high speed asynchronous datapath 162
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems 161
A high-speed energy-efficient 64-bit reconfigurable binary adder 160
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 158
A new reconfigurable coarse-grain architecture for multimedia applications 155
56-bit self-timed adder for high speed asynchronous datapaths 154
Multimodal background subtraction for high-performance embedded systems 148
An efficient hardware-oriented single-pass approach for connected component analysis 148
A high flexible early-late gate bit synchronizer in FPGA-based software defined radios 148
64-bit reconfigurable adder for low power media processing 143
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 143
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 140
A high flexible 8-bit and 16-bit SIMD soft microcontroller for FPGAs 139
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 139
A Low-Power Sub-Nanosecond Standard-Cells Based Adder 138
A new low-power high-speed single-clock-cycle binary comparator 138
A Microchip Integrated Sensor for the Monitoring of High Concentration Photo-voltaic Solar Modules 138
An efficient connected component labeling architecture for embedded systems 138
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 137
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 137
A microchip integrated wireless sensor for the monitoring of high concentration photo-voltaic solar cells 136
A matrix product coprocessor for FPGA embedded soft processors 136
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 135
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 134
High speed division and square root modules for asynchronous datapaths 131
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 129
A novel background subtraction method based on color invariants and grayscale levels 129
An efficient wavelet image encoder for FPGA-based design 129
A new charge-pump based countermeasure against differential power analysis 129
A New High Performance Circuit for Statistical Carry Lookahead Addition 129
Low-power split-path data-driven dynamic logic 128
Techniques for leakage energy reduction in deep submicrometer cache memories 126
A parallel connected component labeling architecture for heterogeneous systems-on-chip 125
An explainable embedded neural system for on-board ship detection from optical satellite imagery 124
A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations 123
High speed self-timed pipelined datapath for square rooting 122
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 122
Comparative analysis of yield optimized pulsed flip-flops 120
Design of Real-Time FPGA-based Embedded System for Stereo Vision 120
Learning Style Identification by CHAEA Junior Questionnaire and Artificial Neural Network Method: A Case Study 120
An efficient convolution engine based on the à-trous spatial pyramid pooling 120
Variable precision arithmetic circuits for FPGA-based multimedia processors 119
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 119
Low-Power Level Shifter for Multi-Supply Voltage Designs 118
Design of a real-time face detection architecture for heterogeneous systems-on-chips 118
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 117
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 117
Accurate power estimation model for CMOS adders optimization 115
Low bit rate image compression core for onboard space applications 115
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals 115
A Fast Carry Chain Adder for Virtex-5 FPGAs 114
Hybrid carry-select statistical carry look-ahead adder 113
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits 113
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing 111
New methodology for the design of efficient binary addition circuits in QCA 111
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 110
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology 110
Adaptive Census transform: A novel hardware-oriented stereovision algorithm 109
A new type of fast, low-cost binary adder 109
Educational design of high-performance arithmetic circuits on FPGA 109
An efficient self-timed adder realized using conventional CMOS standard cells 109
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation 109
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 108
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 107
Educational Design of high performance arithmetic circuits 107
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 107
Multimodal background subtraction for high-performance embedded systems 107
Efficient deconvolution architecture for heterogeneous systems-on-chip 107
Design of efficient QCA multiplexers 106
Efficient VLSI implementation of statistical carry lookahead adder 105
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 105
New high performance circuit for statistical carry lookahead addition 104
An Efficient Hardware-Oriented Stereo Matching Algorithm 104
Fast, low-cost adders using carry-strength signals 104
High speed self-timed pipelined datapath for square root 103
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 103
Energy‐efficient architecture for CNNs inference on heterogeneous FPGA 103
Design of a Low-Power Super-Resolution Architecture for Virtual Reality Wearable Devices 102
VLSI circuits for low-power high-speed asynchronous addition 102
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor 102
High speed division and square root modules for asynchronous datapath 101
Area-delay efficient binary adders in QCA 101
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines 101
Area-time-power tradeoff in VLSI cellular arrays implementations 100
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 100
Embedded surveillance system using background subtraction and Raspberry Pi 100
Fast and energy-efficient Manchester Carry by-pass adders 100
An embedded machine vision system for an in-line quality check of assembly processes 100
Design of Approximate Bilateral Filters for Image Denoising on FPGAs 99
Circuito integrato digitale per operazioni di somma binaria in sistemi asincroni ad alta velocità 99
Designing High-Speed Adders in Power-Constrained Environments 98
Design of Efficient BCD adders in Quantum Dot Cellular Automata 97
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates 97
Design of efficient binary comparators in Quantum-Dot Cellular Automata 97
High performance square rooting circuit using hybrid radix-2 adders 96
Totale 12.222
Salva come PNG Salva come JPEG
Categoria #
all - tutte 111.282
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 111.282
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021139 0 0 0 0 0 0 0 0 0 0 0 139
2021/20221.530 12 201 1 92 155 47 10 278 17 15 248 454
2022/20231.884 200 138 24 221 260 223 7 330 244 72 84 81
2023/2024965 130 48 83 44 44 64 21 81 104 30 82 234
2024/20252.856 91 472 74 119 235 120 96 215 418 113 277 626
2025/20268.895 1.041 433 742 1.013 1.532 548 901 432 642 735 416 460
Totale 19.256