IRIS
PERRI, Stefania
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
NA - Nord America 4.153
EU - Europa 2.298
AS - Asia 395
AF - Africa 188
SA - Sud America 10
OC - Oceania 8
Continente sconosciuto - Info sul continente non disponibili 7
Totale 7.059
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 4.029
UA - Ucraina 1.093
DE - Germania 607
SE - Svezia 248
CN - Cina 186
SN - Senegal 180
IT - Italia 176
TR - Turchia 152
CA - Canada 123
FI - Finlandia 50
BE - Belgio 36
AT - Austria 29
GB - Regno Unito 21
FR - Francia 13
SG - Singapore 12
IN - India 11
AU - Australia 8
EG - Egitto 7
EU - Europa 7
HK - Hong Kong 7
KR - Corea 5
IL - Israele 4
PK - Pakistan 4
PL - Polonia 4
TW - Taiwan 4
AR - Argentina 3
ID - Indonesia 3
NL - Olanda 3
PE - Perù 3
BD - Bangladesh 2
BR - Brasile 2
GR - Grecia 2
JP - Giappone 2
LU - Lussemburgo 2
LV - Lettonia 2
MK - Macedonia 2
RU - Federazione Russa 2
AL - Albania 1
AZ - Azerbaigian 1
CH - Svizzera 1
CL - Cile 1
EC - Ecuador 1
ES - Italia 1
HR - Croazia 1
IM - Isola di Man 1
LT - Lituania 1
MY - Malesia 1
PA - Panama 1
RO - Romania 1
RS - Serbia 1
SA - Arabia Saudita 1
ZW - Zimbabwe 1
Totale 7.059
Salva come PNG Salva come JPEG
Città #
Chandler 854
Jacksonville 732
Dearborn 374
San Mateo 237
Dakar 180
Lawrence 169
Roxbury 169
Izmir 141
Des Moines 116
Ann Arbor 109
Ottawa 106
Rende 87
Cambridge 85
Shanghai 75
Bremen 74
Inglewood 60
Ogden 58
Beijing 49
Helsinki 49
Ashburn 47
Grafing 37
Brooklyn 36
Brussels 36
New York 36
Wilmington 33
Boardman 26
Seattle 25
Vienna 23
San Francisco 18
Nanjing 12
Toronto 11
Norwalk 10
Bari 8
Milan 8
Los Angeles 7
Redmond 7
Duncan 6
Frankfurt am Main 5
Seoul 5
Woodbridge 5
Canberra 4
Central 4
Changsha 4
Dayton 4
Falkenstein 4
Falls Church 4
Guangzhou 4
Hefei 4
Jinan 4
Mascalucia 4
Naples 4
Tappahannock 4
Amsterdam 3
Chicago 3
Edinburgh 3
Giza 3
Houston 3
London 3
Melbourne 3
Nanchang 3
Ningbo 3
Palermo 3
Rizziconi 3
Santa Clara 3
Taizhou 3
Taxila 3
Tel Aviv 3
Warsaw 3
Assiut 2
Bandung 2
Berlin 2
Bologna 2
Canosa di Puglia 2
Catanzaro 2
Chengdu 2
Chiaravalle Centrale 2
Chiclayo 2
Chongqing 2
Corbeil-Essonnes 2
Crotone 2
Dhaka 2
Florence 2
Fuzhou 2
Haikou 2
Hebei 2
Hesperange 2
Hong Kong 2
Hsinchu 2
Hyderabad 2
Ladispoli 2
Le Pré-saint-gervais 2
Magliano Alpi 2
Markham 2
Norrköping 2
Scilla 2
Skopje 2
Sudbury 2
Taipei 2
Thessaloniki 2
Turin 2
Totale 4.285
Salva come PNG Salva come JPEG
Nome #
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 78
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 70
A high-performance fully reconfigurable FPGA-based 2D convolution processor 70
A FPSoC for wavelet-based image compression 70
High speed division and square root modules for asynchronous datapaths 65
A 56-bit self-timed adder for high speed asynchronous datapath 65
56-bit self-timed adder for high speed asynchronous datapaths 65
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 64
A Matrix Product Accelerator for Field Programmable Systems on Chip 64
Comparative analysis of yield optimized pulsed flip-flops 64
Low-power split-path data-driven dynamic logic 62
A high flexible early-late gate bit synchronizer in FPGA-based software defined radios 62
A Microchip Integrated Sensor for the Monitoring of High Concentration Photo-voltaic Solar Modules 62
A novel background subtraction method based on color invariants and grayscale levels 61
A high flexible 8-bit and 16-bit SIMD soft microcontroller for FPGAs 61
An efficient connected component labeling architecture for embedded systems 61
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 61
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 61
Multimodal background subtraction for high-performance embedded systems 60
Techniques for leakage energy reduction in deep submicrometer cache memories 58
High speed self-timed pipelined datapath for square root 58
High speed self-timed pipelined datapath for square rooting 58
A new type of fast, low-cost binary adder 58
A high-speed energy-efficient 64-bit reconfigurable binary adder 58
A New High Performance Circuit for Statistical Carry Lookahead Addition 58
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 58
A microchip integrated wireless sensor for the monitoring of high concentration photo-voltaic solar cells 57
A new charge-pump based countermeasure against differential power analysis 57
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 57
Variable precision arithmetic circuits for FPGA-based multimedia processors 56
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 56
Low-Power Level Shifter for Multi-Supply Voltage Designs 56
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 54
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 54
High performance square rooting circuit using hybrid radix-2 adders 53
A matrix product coprocessor for FPGA embedded soft processors 52
Designing Fast Convolutional Engines for Deep Learning Applications 52
Design of Real-Time FPGA-based Embedded System for Stereo Vision 52
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology 52
VLSI circuits for low-power high-speed asynchronous addition 51
Hybrid carry-select statistical carry look-ahead adder 51
Adaptive Census transform: A novel hardware-oriented stereovision algorithm 51
Design of efficient QCA multiplexers 51
A Low-Power Sub-Nanosecond Standard-Cells Based Adder 51
64-bit reconfigurable adder for low power media processing 51
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 51
A Fast Carry Chain Adder for Virtex-5 FPGAs 50
An embedded machine vision system for an in-line quality check of assembly processes 50
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 49
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 49
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 49
Design of Efficient BCD adders in Quantum Dot Cellular Automata 49
Accurate power estimation model for CMOS adders optimization 49
A new low-power high-speed single-clock-cycle binary comparator 49
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing 49
Low bit rate image compression core for onboard space applications 49
A new reconfigurable coarse-grain architecture for multimedia applications 48
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 48
Color Invariant Study for Background Subtraction 45
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 45
Designing High-Speed Adders in Power-Constrained Environments 45
Efficient VLSI implementation of statistical carry lookahead adder 45
High speed division and square root modules for asynchronous datapath 44
Efficient Recursive Multiply Architecture for FPGAs 44
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 44
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates 44
Area-time-power tradeoff in VLSI cellular arrays implementations 43
An efficient hardware-oriented single-pass approach for connected component analysis 43
An Efficient Hardware-Oriented Stereo Matching Algorithm 43
Approximate Multipliers with Dynamic Truncation for Energy Reduction via Graceful Quality Degradation 43
Learning Style Identification by CHAEA Junior Questionnaire and Artificial Neural Network Method: A Case Study 43
An efficient wavelet image encoder for FPGA-based design 42
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor 42
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation 42
Area-delay efficient binary adders in QCA 41
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits 41
Embedded surveillance system using background subtraction and Raspberry Pi 41
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator 41
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 41
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 41
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations 41
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing 40
Design and Implementation of a 90nm low bit-rate image compression core 40
Educational design of high-performance arithmetic circuits on FPGA 40
Performance comparison between static and dynamic CMOS logic implementations of a pipelined square-rooting circuit 40
Editorial for the special issue on “quantum-dot cellular automata (QCA) and low power application” 40
A parallel connected component labeling architecture for heterogeneous systems-on-chip 40
Fast-squarer circuits using 3-bit-scan without overlapping bits 39
Design of 3 : 1 multiplexer standard cell 39
An Hybrid Carry Select Statistical Carry Look-Ahead Adder 39
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing 39
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath 39
Circuito integrato digitale per operazioni di somma binaria in sistemi asincroni ad alta velocità 39
Energy‐efficient architecture for CNNs inference on heterogeneous FPGA 39
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 39
Fast, low-cost adders using carry-strength signals 38
Impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis 38
Fast and energy-efficient Manchester Carry by-pass adders 38
Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs 38
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems 38
Totale 5.011
Salva come PNG Salva come JPEG
Categoria #
all - tutte 48.982
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 48.982
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019147 0 0 0 0 0 0 0 0 0 0 143 4
2019/20201.505 155 148 0 152 89 390 102 169 30 34 156 80
2020/20211.190 196 2 151 162 6 150 11 177 19 168 9 139
2021/20221.530 12 201 1 92 155 47 10 278 17 15 248 454
2022/20231.884 200 138 24 221 260 223 7 330 244 72 84 81
2023/2024653 130 48 83 44 44 64 21 81 104 30 4 0
Totale 7.193