IRIS
PERRI, Stefania
 Distribuzione geografica
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Continente #
NA - Nord America 5.736
AS - Asia 4.911
EU - Europa 2.952
SA - Sud America 1.442
AF - Africa 317
OC - Oceania 11
Continente sconosciuto - Info sul continente non disponibili 9
Totale 15.378
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Nazione #
US - Stati Uniti d'America 5.511
SG - Singapore 2.255
UA - Ucraina 1.111
BR - Brasile 1.103
CN - Cina 976
DE - Germania 703
VN - Vietnam 601
IT - Italia 358
HK - Hong Kong 324
SE - Svezia 253
SN - Senegal 182
TR - Turchia 168
KR - Corea 158
CA - Canada 143
AR - Argentina 131
FI - Finlandia 129
IN - India 78
FR - Francia 66
IQ - Iraq 61
BD - Bangladesh 60
GB - Regno Unito 59
RU - Federazione Russa 52
ID - Indonesia 51
EC - Ecuador 50
AT - Austria 43
MX - Messico 43
ZA - Sudafrica 42
CO - Colombia 38
BE - Belgio 36
PK - Pakistan 30
CL - Cile 28
PL - Polonia 28
PY - Paraguay 28
VE - Venezuela 28
NL - Olanda 25
EG - Egitto 23
MA - Marocco 22
ES - Italia 20
JO - Giordania 19
PE - Perù 14
UY - Uruguay 14
JP - Giappone 13
IL - Israele 12
UZ - Uzbekistan 12
DO - Repubblica Dominicana 10
ET - Etiopia 10
KE - Kenya 10
KG - Kirghizistan 10
NP - Nepal 10
TN - Tunisia 10
KZ - Kazakistan 9
SA - Arabia Saudita 9
AU - Australia 8
AZ - Azerbaigian 7
CZ - Repubblica Ceca 7
EU - Europa 7
RS - Serbia 7
AE - Emirati Arabi Uniti 6
AL - Albania 6
CR - Costa Rica 6
DZ - Algeria 6
LB - Libano 6
AM - Armenia 5
BO - Bolivia 5
CH - Svizzera 5
LT - Lituania 5
OM - Oman 5
PA - Panama 5
RO - Romania 5
BG - Bulgaria 4
BY - Bielorussia 4
IR - Iran 4
MK - Macedonia 4
NI - Nicaragua 4
TW - Taiwan 4
BW - Botswana 3
CI - Costa d'Avorio 3
GR - Grecia 3
GT - Guatemala 3
HR - Croazia 3
KW - Kuwait 3
LV - Lettonia 3
MY - Malesia 3
AO - Angola 2
BA - Bosnia-Erzegovina 2
BB - Barbados 2
GE - Georgia 2
HN - Honduras 2
IE - Irlanda 2
JM - Giamaica 2
KI - Kiribati 2
LK - Sri Lanka 2
LU - Lussemburgo 2
PH - Filippine 2
PT - Portogallo 2
SV - El Salvador 2
SY - Repubblica araba siriana 2
XK - ???statistics.table.value.countryCode.XK??? 2
BF - Burkina Faso 1
BH - Bahrain 1
Totale 15.360
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Città #
Singapore 881
Chandler 854
Jacksonville 732
Boardman 398
Dallas 397
Dearborn 374
Hong Kong 316
Beijing 259
San Mateo 237
Ho Chi Minh City 234
Dakar 182
Lawrence 169
Roxbury 169
Ashburn 163
Seoul 157
Izmir 142
Hefei 141
Shanghai 139
Hanoi 124
Des Moines 117
Ann Arbor 109
Ottawa 107
Rende 104
Helsinki 98
Cambridge 85
São Paulo 81
Bremen 74
Inglewood 60
Ogden 58
The Dalles 57
Council Bluffs 51
Munich 51
New York 51
Columbus 47
Brooklyn 46
Los Angeles 44
Grafing 37
San Jose 37
Brussels 36
Milan 35
Rio de Janeiro 34
Wilmington 33
Haiphong 31
Catanzaro 30
Tianjin 28
Santa Clara 27
Turku 27
Vienna 27
Seattle 26
San Francisco 25
Guangzhou 24
Quito 21
Warsaw 21
Da Nang 20
Baghdad 19
Biên Hòa 18
Amman 17
Belo Horizonte 17
Asunción 16
Johannesburg 16
Toronto 16
Campinas 15
Curitiba 15
Dhaka 15
Frankfurt am Main 15
Bari 14
Falkenstein 14
Chennai 13
Guarulhos 13
Guayaquil 13
Mexico City 13
Naples 13
Porto Alegre 13
Shenzhen 13
Hải Dương 12
Juiz de Fora 12
Nanjing 12
Amsterdam 11
Brasília 11
Chicago 11
Lima 11
London 11
Montevideo 11
Nuremberg 11
Rome 11
Thái Bình 11
Betim 10
Can Tho 10
Fortaleza 10
Joinville 10
Norwalk 10
Tokyo 10
Addis Ababa 9
Bishkek 9
Bogotá 9
Buenos Aires 9
Maracaibo 9
Nairobi 9
Ninh Bình 9
Quảng Ngãi 9
Totale 8.392
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Nome #
A high-performance fully reconfigurable FPGA-based 2D convolution processor 166
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 140
A FPSoC for wavelet-based image compression 139
A 56-bit self-timed adder for high speed asynchronous datapath 138
A high-speed energy-efficient 64-bit reconfigurable binary adder 137
A Matrix Product Accelerator for Field Programmable Systems on Chip 131
56-bit self-timed adder for high speed asynchronous datapaths 130
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations 130
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 129
A high flexible early-late gate bit synchronizer in FPGA-based software defined radios 128
A high flexible 8-bit and 16-bit SIMD soft microcontroller for FPGAs 128
An efficient hardware-oriented single-pass approach for connected component analysis 127
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 122
A new reconfigurable coarse-grain architecture for multimedia applications 122
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 122
A Low-Power Sub-Nanosecond Standard-Cells Based Adder 118
A new charge-pump based countermeasure against differential power analysis 118
A new low-power high-speed single-clock-cycle binary comparator 118
A matrix product coprocessor for FPGA embedded soft processors 118
High speed division and square root modules for asynchronous datapaths 116
A microchip integrated wireless sensor for the monitoring of high concentration photo-voltaic solar cells 116
64-bit reconfigurable adder for low power media processing 116
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 115
A Microchip Integrated Sensor for the Monitoring of High Concentration Photo-voltaic Solar Modules 115
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 115
A New High Performance Circuit for Statistical Carry Lookahead Addition 115
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 113
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 112
A novel background subtraction method based on color invariants and grayscale levels 111
Multimodal background subtraction for high-performance embedded systems 107
An efficient connected component labeling architecture for embedded systems 107
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 107
High speed self-timed pipelined datapath for square rooting 106
Techniques for leakage energy reduction in deep submicrometer cache memories 104
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 104
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 102
An efficient wavelet image encoder for FPGA-based design 102
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 102
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 102
Learning Style Identification by CHAEA Junior Questionnaire and Artificial Neural Network Method: A Case Study 101
An explainable embedded neural system for on-board ship detection from optical satellite imagery 99
Variable precision arithmetic circuits for FPGA-based multimedia processors 98
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 98
A Fast Carry Chain Adder for Virtex-5 FPGAs 97
Low-Power Level Shifter for Multi-Supply Voltage Designs 97
Comparative analysis of yield optimized pulsed flip-flops 97
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems 97
Accurate power estimation model for CMOS adders optimization 96
A new type of fast, low-cost binary adder 96
A parallel connected component labeling architecture for heterogeneous systems-on-chip 96
An efficient convolution engine based on the à-trous spatial pyramid pooling 95
An Efficient Hardware-Oriented Stereo Matching Algorithm 94
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing 94
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology 94
Design of Real-Time FPGA-based Embedded System for Stereo Vision 93
Low-power split-path data-driven dynamic logic 92
Fast, low-cost adders using carry-strength signals 92
Hybrid carry-select statistical carry look-ahead adder 91
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits 91
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 91
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 91
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines 90
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation 90
Adaptive Census transform: A novel hardware-oriented stereovision algorithm 89
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 88
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 88
High speed self-timed pipelined datapath for square root 88
Low bit rate image compression core for onboard space applications 88
Area-delay efficient binary adders in QCA 87
Educational Design of high performance arithmetic circuits 87
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 87
VLSI circuits for low-power high-speed asynchronous addition 86
Educational design of high-performance arithmetic circuits on FPGA 86
New methodology for the design of efficient binary addition circuits in QCA 86
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 86
Efficient VLSI implementation of statistical carry lookahead adder 86
Multimodal background subtraction for high-performance embedded systems 86
Energy‐efficient architecture for CNNs inference on heterogeneous FPGA 86
Design of efficient QCA multiplexers 85
Design of Efficient BCD adders in Quantum Dot Cellular Automata 85
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 85
An embedded machine vision system for an in-line quality check of assembly processes 85
Area-time-power tradeoff in VLSI cellular arrays implementations 83
High speed division and square root modules for asynchronous datapath 83
Embedded surveillance system using background subtraction and Raspberry Pi 83
An efficient self-timed adder realized using conventional CMOS standard cells 83
Stereo vision architecture for heterogeneous systems-on-chip 83
New high performance circuit for statistical carry lookahead addition 82
Circuito integrato digitale per operazioni di somma binaria in sistemi asincroni ad alta velocità 82
Designing High-Speed Adders in Power-Constrained Environments 82
Designing Fast Convolutional Engines for Deep Learning Applications 82
Design of Approximate Bilateral Filters for Image Denoising on FPGAs 81
Fast and energy-efficient Manchester Carry by-pass adders 81
Approximate Multipliers with Dynamic Truncation for Energy Reduction via Graceful Quality Degradation 80
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals 80
Design of a Low-Power Super-Resolution Architecture for Virtual Reality Wearable Devices 79
High performance square rooting circuit using hybrid radix-2 adders 79
Color Invariant Study for Background Subtraction 79
Sad-Based Stereo Matching Circuit for FPGAs 79
Fast-squarer circuits using 3-bit-scan without overlapping bits 78
Totale 10.021
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Categoria #
all - tutte 101.424
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 101.424
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021673 0 0 0 0 0 150 11 177 19 168 9 139
2021/20221.530 12 201 1 92 155 47 10 278 17 15 248 454
2022/20231.884 200 138 24 221 260 223 7 330 244 72 84 81
2023/2024965 130 48 83 44 44 64 21 81 104 30 82 234
2024/20252.856 91 472 74 119 235 120 96 215 418 113 277 626
2025/20265.198 1.041 433 742 1.013 1.532 437 0 0 0 0 0 0
Totale 15.559