Positive bias temperature instability (PBTI) in nMOSFETs with ultra thin HfSiON gate dielectrics has been investigated. We propose that PBTI is due to electron trapping in the high-k dielectrics layer and we present results of measurements performed at different bias condition and temperatures consistent with the proposed model. Extrapolated lifetimes indicate that PBTI in HfSiON gate dielectrics severely impacts the reliability of CMOS devices only in the case of Hf rich-layers.
Positive bias temperature instability (PBTI) in nMOSFETs with ultra thin HfSiON gate dielectrics has been investigated. We propose that PBTI is due to electron trapping in the high-k dielectrics layer and we present results of measurements performed at different bias condition and temperatures consistent with the proposed model. Extrapolated lifetimes indicate that PBTI in HfSiON gate dielectrics severely impacts the reliability of CMOS devices only in the case of Hf rich-layers.
Positive Bias Temperature Instability in nMOSFETs with ultra-thin Hf-silicate gate dielectrics
CRUPI, Felice;PACE, Calogero;COCORULLO, Giuseppe;
2005-01-01
Abstract
Positive bias temperature instability (PBTI) in nMOSFETs with ultra thin HfSiON gate dielectrics has been investigated. We propose that PBTI is due to electron trapping in the high-k dielectrics layer and we present results of measurements performed at different bias condition and temperatures consistent with the proposed model. Extrapolated lifetimes indicate that PBTI in HfSiON gate dielectrics severely impacts the reliability of CMOS devices only in the case of Hf rich-layers.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
