In the above paper [1, p. 2580], Tables IV and VI must be replaced. Due to a production error, the correct version of Table IV was not included, and Table VI contained an error in the PM value for NMC topology (6th row, 3th column). Following are the correct versions of Tables IV and VI. Manuscript received June 21, 2010. Date of publication July 01, 2010; date of current version July 16, 2010.
Corrections to Settling Time Optimization for Three-Stage CMOS Amplifier Topologies (vol 56, pg 2569, 2009)
CAPPUCCINO, Gregorio;COCORULLO G.
2010-01-01
Abstract
In the above paper [1, p. 2580], Tables IV and VI must be replaced. Due to a production error, the correct version of Table IV was not included, and Table VI contained an error in the PM value for NMC topology (6th row, 3th column). Following are the correct versions of Tables IV and VI. Manuscript received June 21, 2010. Date of publication July 01, 2010; date of current version July 16, 2010.File in questo prodotto:
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