The impact of high-order integrator dynamics on switched-capacitor sigma-delta modulator performances is investigated in this paper. An advanced generic integrator-settling model to take into account high-order dynamic effects is presented and validated by means of transistor-level simulations of circuits implemented in a commercial 0.35 m CMOS technology. The model is used through the paper to carry out an exhaustive behavioral analysis for second-order single-bit sigma-delta modulator characterized by first-, second-, and third-order integrator dynamics, showing how high-order poles and zeros can affect the sigma-delta modulator characteristics remarkably. The proposed analysis provides useful guidelines to fix a convenient integrator poles/zeros placement in order to achieve an effective sigma-delta modulator design flow.
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances
CAPPUCCINO, Gregorio;COCORULLO, Giuseppe
2010-01-01
Abstract
The impact of high-order integrator dynamics on switched-capacitor sigma-delta modulator performances is investigated in this paper. An advanced generic integrator-settling model to take into account high-order dynamic effects is presented and validated by means of transistor-level simulations of circuits implemented in a commercial 0.35 m CMOS technology. The model is used through the paper to carry out an exhaustive behavioral analysis for second-order single-bit sigma-delta modulator characterized by first-, second-, and third-order integrator dynamics, showing how high-order poles and zeros can affect the sigma-delta modulator characteristics remarkably. The proposed analysis provides useful guidelines to fix a convenient integrator poles/zeros placement in order to achieve an effective sigma-delta modulator design flow.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
