Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates

An efficient technique for designing high-performance logic circuits operating in sub-threshold region isproposed. A simple gate-level body biasing circuit is exploited to change dynamically the threshold voltageof transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switchingwhile maintaining energy efficiency.If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designedas described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previouslyproposed sub-threshold approaches.