Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies

This paper presents a novel approach to design high-speed low-power parallel-prefix adder trees. Subcircuitstypically used in the design of parallel-prefix trees are deeply analyzed and separately optimized.The modules used for computing the group propagate and generate signals have been designed to improvetheir energy-delay behavior in an original way. When the ST 45nm 1V CMOS technology is used, incomparison with conventional implementations, the proposed approach exhibits computational delay withmean value and standard deviation up to 40% and 48% lower, and achieves energy consumption with meanvalue and standard deviation up to 57% and 40% lower.A 32-bit Brent-Kung tree made as proposed here reaches a computational delay lower than 165ps anddissipates 147.4fJ on average.